參數(shù)資料
型號： DSP16210
英文描述： TVS 400W 6.5V UNIDIRECT SMA
中文描述： DSP16210數(shù)字信號處理器
文件頁數(shù)： 36/173頁
文件大小： 2621K
代理商： DSP16210
Data Sheet
July 2000
DSP16210 Digital Signal Processor
36
DRAFT COPY
Lucent Technologies Inc.
Hardware Architecture
(continued)
Enhanced Serial I/O Unit (ESIO)
(continued)
Prior to initializing the input section as described
above, the programmer must configure
ICVV
,
ICSB
0—7
, and
ICSL
0—1
. The write of
ICR
that ini-
tializes the input section must also configure the input
section appropriately (IMODE, IFRMSZ, etc.). Before
changing any input channel attributes (e.g.,
ICVV
,
IMODE), the programmer must first reset the input sec-
tion. Specifically, the programmer must write
ICR
with
the IRESET field (bit 4) set and the ICA field (bit 2)
clear, change the attributes, and then enable the input
section by writing
ICR
with the ICA field (bit 2) set.
In an environment with several different logical channel
sampling lengths, the EIBF generation rate should be
set to the highest serial-to-parallel transfer rate (see
Table 49 on page 96
). Each channel is serviced at its
programmed rate when a full word of input data is pro-
vided. For example, in a system with logical channels
of sample length 1, 2, and 8 bits, the highest serial-to-
parallel transfer rate is every two frames and IFIR
should be programmed to 0 (one EIBF every two
frames). The channels with an 8-bit sample length
should be serviced every EIBF interrupt, the channels
with a 2-bit sample length should be serviced every
four EIBF interrupts, and the channels with a 1-bit sam-
ple length should be serviced every eight EIBF inter-
rupts.
The ITMODE field (bit 9) of
ICR
can override the serial-
to-parallel transfer rate specified by
ICSL
0—1
. When
ITMODE is set to 1, data is transferred from each input
shift register to all sixteen
IDMX
0—15
registers
simultaneously at the programmed IFIR frequency. The
ESIO asserts EIBF for each transfer. It is not necessary
to reset the ESIO prior to changing the ITMODE bit.
Note:
In ITMODE, input data is not necessarily right-
justified in
IDMX
0—15
. The LSB of the data
stream is continuously shifted into the MSB (8-bit
or 16-bit) location of each shift register. The con-
tents of the shift registers are transferred to the
IDMX
0—15
registers at the alternate IFIR fre-
quency.
The logical channels are enabled by programming the
16-bit
ICVV
register. Each bit in this register corre-
sponds to a logical channel, e.g., bit 5 of
ICVV
corre-
sponds to logical channel 5. When a bit in
ICVV
is set,
the ESIO demultiplexes the input data stream for the
corresponding channel. The bits in
ICVV
must be
packed, i.e., channels must be allocated from 0 to 15
with no holes between valid channels. For example, if
ICVV
contains 0x00FF, then logical channels 0—7 are
enabled and demultiplexed. A value of 0x08FF for
ICVV
is invalid because the channels are not packed.
Logical channels must be assigned in increasing input
channel start bit order and must not overlap. For exam-
ple, if channel 4 has a start bit of 48 and a sample
length of 4 bits (
ICSB2
[7:0] = 0x30;
ICSL0
[9:8] = 10),
then channel 5 must have a start bit value greater than
or equal to 52 (48 + 4).
The ESIO reports an input frame error (EIFE) when it is
processing a valid frame and an input frame sync is
detected before the number of bits in the programmed
frame length (IFRMSZ in
ICR
) have been sampled. If
an EIFE interrupt occurs, the DSP program should
reset the input section by writing
ICR
with the IRESET
bit set.
Output Section
The control registers in the ESIO output section are the
output control register (
OCR
), the output channel start
bit registers (
OCSB
0—7
), the output channel sample
length registers (
OCSL
0—1
), and the output channel
valid vector register (
OCVV
). The data registers are
OMX
0—15
. All the ESIO output section registers are
16 bits and are memory mapped as illustrated in
Table 12.
Table 12. ESIO Memory Map (Output Section)
Memory
Address
0xE0020
OMX0
W
0xE0021
OMX1
W
0xE0022
OMX2
W
0xE0023
OMX3
W
0xE0024
OMX4
W
0xE0025
OMX5
W
0xE0026
OMX6
W
0xE0027
OMX7
W
0xE0028
OMX8
W
0xE0029
OMX9
W
0xE002A
OMX10
W
0xE002B
OMX11
W
0xE002C
OMX12
W
0xE002D
OMX13
W
0xE002E
OMX14
W
0xE002F
OMX15
W
Register R/W
This column indicates whether the register is readable (R) and/or
writable (W).
Memory
Address
0xE0030
0xE0031
0xE0032
0xE0033
0xE0034
0xE0035
0xE0036
0xE0037
0xE0038
0xE0039
0xE003A
0xE003B
0xE003C
0xE003D
0xE003E
0xE003F
Register R/W
OCSB0
OCSB1
OCSB2
OCSB3
OCSB4
OCSB5
OCSB6
OCSB7
OCSL0
OCSL1
OCR
OCVV
RESERVED
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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