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參數(shù)資料
| 型號： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號處理器 |
| 文件頁數(shù)： | 32/173頁 |
| 文件大小： | 2621K |
| 代理商： | DSP16210 |
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Data Sheet
July 2000
DSP16210 Digital Signal Processor
32
DRAFT COPY
Lucent Technologies Inc.
Hardware Architecture
(continued)
Enhanced Serial I/O (ESIO) Unit
The ESIO is a programmable, hardware-managed,
double-buffered, full-duplex serial I/O port designed to
support glueless multichannel I/O processing on a
TDM (time-division multiplex) highway. It has a 4-pin
input interface (EIFS, EIBC, EDI, and EIBF) and a 5-pin
output interface (EOFS, EOBC, EDO, EOEB, and
EOBE). See
Signal Descriptions beginning on
page 121
for more details. ESIO input and output bit
clocks are passive, i.e., must be provided by an exter-
nal source. Data is transmitted and received in an
LSB-first manner. The ESIO supports two modes of
operation:
1. Simple mode: Serial I/O that has programmable 8-bit
or 16-bit data lengths. The maximum serial data rate
is 26 Mbits/s.
2. Frame mode: Up to 16 logical channels are multi-
plexed and demultiplexed on a standard
256-bit/frame TDM highway or on a
64-/128-/192-bit/frame highway
1
. The sample length
for each channel is individually programmed as 1, 2,
4, or 8 bits corresponding to 8 Kbits/s, 16 Kbits/s,
32 Kbits/s, and 64 Kbits/s for a 2.048 Mbits/s TDM
highway. The maximum supported serial data rate is
8.192 Mbits/s.
The ESIO communicates I/O buffer status to the core
using the input buffer full (EIBF), output buffer empty
(EOBE), input frame error (EIFE), output frame error
(EOFE), and output collision (ECOL) interrupts. The
input buffer full and output buffer empty conditions are
also indicated via the EIBF and EOBE pins. In frame
mode, EIBF and EOBE are based upon the completion
of a programmable number of frames.
The ESIO contains 16 memory-mapped, double-buff-
ered serial-to-parallel input demultiplexer registers
(
IDMX
0—15
). These 16-bit read-only registers can
be configured to demultiplex a maximum of 16 logical
input channels. A logical input channel is a nonoverlap-
ping sequence of consecutive bits (1, 2, 4, or 8) identi-
fied by a starting bit position within the frame.
The ESIO also contains 16 memory-mapped, double-
buffered parallel-to-serial output multiplexer registers
(
OMX
0—15
). These 16-bit write-only registers can
be configured to multiplex a maximum of 16 logical out-
put channels. A logical output channel is a nonoverlap-
ping sequence of consecutive bits (1, 2, 4, or 8)
identified by a starting bit position within the frame.
The ESIO’s serial data output (EDO) supports multi-
master operation and can be configured as open-drain
or 3-state.
Input Section
The control registers in the ESIO input section are the
input control register (
ICR)
, input channel start bit reg-
isters (
ICSB
0—7
)
, input channel start length regis-
ters (
ICSL
0—1
)
, and input channel valid vector
register (
ICVV
). The data registers are
IDMX
0—15
.
All the ESIO input section registers are 16 bits and are
memory-mapped as illustrated in Table 10.
Table 10. ESIO Memory Map (Input Section)
Memory
Address
0xE0000
IDMX0
0xE0001
IDMX1
0xE0002
IDMX2
0xE0003
IDMX3
0xE0004
IDMX4
0xE0005
IDMX5
0xE0006
IDMX6
0xE0007
IDMX7
0xE0008
IDMX8
0xE0009
IDMX9
0xE000A
IDMX10
0xE000B
IDMX11
0xE000C
IDMX12
0xE000D
IDMX13
0xE000E
IDMX14
0xE000F
IDMX15
The input control register
(
ICR
) (
Table 47 on page 95
)
controls the configuration of the input section, including
the selection of simple mode vs. frame mode.
ICVV
(
Table 50 on page 96
)
specifies the number of active
logical channels (one for simple mode and 1 through
16 for frame mode).
ICSB
0—7
(
Table 48 on page 96
)
and
ICSL
0—1
(
Table 49 on page 96
) are used only
in frame mode.
They specify the starting bit position
and the sample length (1, 2, 4, or 8 bits) of each logical
channel.
1. A single DSP16210 can process up to 128 bits/frame (sixteen
8-bit channels).
Register R/W
This column indicates whether the register is readable (R) and/or
writable (W).
Memory
Address
0xE0010
0xE0011
0xE0012
0xE0013
0xE0014
0xE0015
0xE0016
0xE0017
0xE0018
0xE0019
0xE001A
0xE001B
0xE001C
0xE001D
0xE001E
0xE001F
Register R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
ICSB0
ICSB1
ICSB2
ICSB3
ICSB4
ICSB5
ICSB6
ICSB7
ICSL0
ICSL1
ICR
ICVV
RESERVED
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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