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參數(shù)資料
| 型號： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號處理器 |
| 文件頁數(shù)： | 33/173頁 |
| 文件大?。?/td> | 2621K |
| 代理商： | DSP16210 |
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Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
33
Hardware Architecture
(continued)
Enhanced Serial I/O Unit (ESIO)
(continued)
ESIO interrupts are summarized in
Table 14 on
page 41
.
Input Control Signal Conditioning.
As illustrated in
Figure 7, ILEV (bit 3) of the
ICR
register (
Table 47 on
page 95
) selects the polarity of the input bit clock,
EIBC. The modified clock is the input bit clock for the
input section (IBC). The input sync level, ISLEV (bit 5)
of the
ICR
register, selects whether or not the input
frame sync, EIFS, is inverted. If input sync delay
(ISDLY) (bit 6) of the
ICR
register is zero, this modified
signal is the frame sync for the input section (IFS). If
ISDLY is one, the modified signal is first retimed by the
EIBC clock before becoming the frame sync for the
input section (IFS). Figure 8 illustrates the timing of
IFS when ISDLY is one.
Figure 7. Input Control Signal Conditioning
Figure 8. Frame Sync Timing with ILEV = ISLEV = 0
and ISDLY = 1
The rising edge of IFS (captured by the next rising
edge of IBC) indicates that the first bit of the serial input
packet or frame (from EDI) is captured by the falling
edge of IBC. This edge also initializes the internal bit
counter to zero, and every subsequent rising edge of
IBC increments the bit counter. In frame mode, this bit
counter is used by the input control hardware to define
logical channel start points and to detect input frame
errors. See Figure 9.
Figure 9. Input Functional Timing
Simple Input Mode Processing.
The ESIO input
block operates in simple input mode when IMODE
(bit 8) of the
ICR
register is set to 1. In this mode, the
programmer must set the
ICVV
register to 0x0001. The
ESIO disables the input frame error interrupt (EIFE).
In simple mode, the ESIO supports double-buffered
8-bit and 16-bit LSB-first serial operation. Eight-bit
serial operation is selected by setting ISIZE (bit 7) of
the
ICR
register. This right justifies 8-bit input packets,
i.e., the 8-bit data is aligned with bits [7:0] of
IDMX0
.
See
Figure 10 on page 34
for a diagram of the input
demultiplexer structure. Serial input data from EDI is
captured into a serial-to-parallel register by the falling
edge of IBC (illustrated as IBCQ0 in
Figure 10
). After
all programmed bits (8 or 16) have been captured, the
data is transferred to the parallel data register
IDMX0
for future core processing (for example,
a0h = *r0
,
where
r0
points to location 0xE0000).
The ESIO asserts the input buffer full (EIBF) output pin
and the EIBF interrupt after the falling edge of the final
IBC capture clock. The EIBF interrupt and pin are
cleared when the DSP reads the
IDMX0
memory-
mapped register. EIBF is also cleared on device reset
or if the DSP program resets the input section (writes
ICR
with the IRESET field (bit 4) set). The simple mode
input timing diagram (for ILEV = 0, ISLEV = 0,
ISIZE = 0, and ISDLY = 0) is illustrated in
Figure 52 on
page 166
.
EIFS
EIBC
M
U
X
0
1
ISDLY
IFS
IBC
FRAME SYNC
AND
CLOCK
FOR
ESIO
INPUT
SECTION
D
Q
ISLEV
ILEV
EIBC
EIFS
IFS
IBC
IFS
EDI
B
0
B
1
DATA
LATCHED
INTERNAL
BIT COUNTER
CLEARED
DATA
LATCHED
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