參數(shù)資料
型號： DSP16210
英文描述： TVS 400W 6.5V UNIDIRECT SMA
中文描述： DSP16210數(shù)字信號處理器
文件頁數(shù)： 126/173頁
文件大?。?/td> 2621K
代理商： DSP16210
Data Sheet
July 2000
DSP16210 Digital Signal Processor
126
DRAFT COPY
Lucent Technologies Inc.
DSP16210 Boot Routines
There are many subroutines in the IROM of the
DSP16210 that allow the user to perform various func-
tions. The primary function of these routines is to
download code and data to the internal DPRAM and
external memory from the PHIF16 or EMI ports. Other
functions include memory test routines, a routine to
enable or disable the PLL, and reserved production test
routines. Once the downloads and/or other functions
are completed, the user can select a boot routine that
branches to the beginning of either the DPRAM or
EROM memory segment.
After reset with the EXM pin low, the DSP16210 begins
executing from location 0x20000 in IROM, which con-
tains a branch to location 0x20400. The program at this
location configures the parallel host interface port,
PHIF16, for a single, 8-bit Intel style transfer (refer to
Parallel Host Interface (PHIF16) beginning on
page 49
), enables INT3, and leaves the PLL disabled.
The program then waits for a host device interfaced to
the PHIF16 port to write an 8-bit command onto
PB[7:0] and strobe PIDS. The program inputs this
value and decodes it to select the appropriate boot rou-
tine. To terminate any routine, the host can assert the
INT3 pin; otherwise, the routine completes its function.
At the completion or termination (interruption) of a rou-
tine, a value of 0xED is written out the PHIF16 port. In
response to the POBE flag, the host must read this
value from the port in order for the boot code to con-
tinue. The program flow is stalled until this port is read.
After this handshake byte has been read, the PHIF16
port is returned to 8-bit Intelstyle mode and waits for
the next command.
Once the user has completed the routines of interest,
e.g., download of code and data or tested memory, the
host can direct the DSP16210 to begin execution of
user code from either the DPRAM (location 0x00000)
or EROM (location 0x80000) XMAP locations.
Note:
Upon exiting the boot code, the following core
registers are not reinitialized to their reset states
as defined in the DSP16000 Digital Signal Pro-
cessor Core nformation Manual:
inc0
,
rb0
,
re0
,
vbase
,
cloop
,
cstate
. With the exception of the
ioc
and
PHIFC
registers, none of the peripheral
registers are reinitialized to their reset states as
defined in
Table 78 on page 114
. It is recom-
mended that the user code immediately globally
disable interrupts by executing a
di
instruction
and clear all pending interrupts by clearing
ins
(
ins = 0xfffff
).
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