參數(shù)資料
型號: DSP16210
英文描述: TVS 400W 6.5V UNIDIRECT SMA
中文描述: DSP16210數(shù)字信號處理器
文件頁數(shù): 10/173頁
文件大?。?/td> 2621K
代理商: DSP16210
Data Sheet
July 2000
DSP16210 Digital Signal Processor
10
DRAFT COPY
Lucent Technologies Inc.
Hardware Architecture
(continued)
DSP16210 Architectural Overview
(continued)
Figure 1. DSP16210 Block Diagram
ioc
VEC0 corresponds to IOBIT7, VEC1 corresponds to IOBIT6, VEC2 corresponds to IOBIT5, and VEC3 corresponds to IOBIT4.
These registers are not directly program accessible.
§ These registers are accessible through pins only.
DSP16000 CORE
INT[3:0]
CKI
CKO
TRAP
IACK
READY
ERAMHI
RSTB
STOP
INTERRUPT
LOGIC
powerc
pllc
CLOCK SELECTION
AND SYNTHESIS (PLL)
TDO
TDI
TCK
TMS
jiob
ID
§
JTAG
HDS
BOUNDARY SCAN
§
TRST
YAB
YDB
XDB
XAB
DPRAM
60K x 16
BANKS 1—60
IROM
8K x 16
timer0c
timer0
TIMER0
SSIO
SSIOC
DI
ICK
ILD
IBF
DO
OCK
OLD
OBE
DOEN
IORAM1
1K x 16
SSDX(in)
SSDX(out)
RWN
EXM
IO
EROM
ERAM
ERAMLO
AB[15:0]
DB[15:0]
EDI
EIFS
EIBC
EIBF
EOEB
IDMX
0—15
ICSB
0—7
ICSL
0—1
ICR
ICVV
ESIO
PSTAT
§
PHIFC
PHIF16
IORAM0
1K x 16
PB[15:0]
PIDS
PODS
PCSN
PSTAT
PBSEL
MIOU0
mcmd0
miwp0
morp0
PDX(in)
PDX(out)
PIBF
POBE
OMX
0—15
OCSB
0—7
OCSL
0—1
OCR
OCVV
EOBE
EDO
EOFS
EOBC
SYNC
timer1c
timer1
TIMER1
VEC[3:0]
MIOU1
mcmd1
miwp1
morp1
EXTERNAL
MEMORY
INTERFACE
mwait
IDB
EDB
EAB
IOBIT[7:4]/
VEC[3:0]
IOBIT[3:0]
CLK
32
20
32
20
10
16
sbit
cbit
BIO
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