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參數(shù)資料
| 型號(hào)： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 50/173頁(yè) |
| 文件大小： | 2621K |
| 代理商： | DSP16210 |
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Data Sheet
July 2000
DSP16210 Digital Signal Processor
50
DRAFT COPY
Lucent Technologies Inc.
Hardware Architecture (continued)
Parallel Host Interface (PHIF16)
(continued)
The function of the pins PIDS and PODS is program-
mable to support both the Inteland Motorolaprotocols.
The PCSN pin is an input that, when low, acts as a
chip-select to enable PIDS and PODS (or PRWN and
PDS, depending on the protocol used). If PCSN is low,
the assertion of PIDS and PODS by an external device
causes the PHIF16 to recognize a host request. If
MIOU0 has been properly programmed, it responds to
the host request by either filling
PDX
(out) or emptying
PDX
(in). While PCSN is high, the DSP16210 ignores
any activity on PIDS and/or PODS. If a DSP16210 is
intended to be continuously accessed through the
PHIF16 port, PCSN should be grounded.
Programmability
The PHIF16 external interface is configured for 8-bit or
16-bit external operation using bit 7 of the
PHIFC
regis-
ter (PCFIG).
In the 16-bit external configuration, every completion of
an input (host) or output (MIOU0) transaction asserts
the external PIBF or POBE conditions.
In the 8-bit external configuration, the PHIF16 interface
is programmed for 8-bit or 16-bit logical data transfers
using bit 0, PMODE, of the
PHIFC
register. Setting
PMODE selects 16-bit logical transfer mode. An input
pin controlled by the host, PBSEL, determines an
access of either the high or low byte. The assertion
level of the PBSEL input pin is configurable in software
using bit 3 of the
PHIFC
register, PBSELF.
Table 22 on
page 51
summarizes the port's output functionality as
controlled by the PSTAT and PBSEL pins and the
PBSELF and PMODE fields.
Table 23 on page 51
sum-
marizes the port’s input functionality.
In the 8-bit external configuration and 16-bit logical
mode, PHIF16 assertion of the PIBF and POBE flags is
based on the status of the PBSELF bit in the
PHIFC
register.
I
If PBSELF is zero, the PIBF and POBE flags are set
after the high byte is transferred.
I
If PBSELF is one, the flags are set after the low byte
is transferred.
In the 8-bit external configuration and 8-bit logical
mode, only the low byte is accessed, and every com-
pletion of an input or output access sets PIBF or
POBE.
Bit 1 of the
PHIFC
register, PSTROBE, configures the
port to operate either with an Intelprotocol where only
the chip select (PCSN) and either of the data strobes
(PIDS or PODS) are needed to make an access, or
with a Motorolaprotocol where the chip select (PCSN),
a data strobe (PDS), and a read/write strobe (PRWN)
are needed. PIDS and PODS are negative assertion
data strobes while the assertion level of PDS is pro-
grammable through bit 2, PSTRB, of the
PHIFC
regis-
ter.
Finally, the assertion level of the output pins, PIBF and
POBE, is controlled through bit 4, PFLAG. When
PFLAG is set low, PIBF and POBE output pins have
positive assertion levels. By setting bit 5, PFLAGSEL,
the logical OR of PIBF and POBE flags (positive asser-
tion) is seen at the output pin PIBF. By setting bit 6 in
PHIFC
, PSOBEF, the polarity of the POBE flag in the
status register,
PSTAT
, is changed. PSOBEF has no
effect on the POBE pin.
PHIFC
is programmed through MIOU0.
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