Data Sheet
July 2000
DSP16210 Digital Signal Processor
132
DRAFT COPY
Lucent Technologies Inc.
DSP16210 Boot Routines
(continued)
Commands
(continued)
Table 81. Command Encoding for Boot Routines
(continued)
0x3A
0x7A
0xBA
0x1F
0x5F
0x9F
0xDF
0x1E
0x5E
0x9E
0xDE
0x3C
0x7C
0xBC
0xFC
0x3E
—
—
—
—
—
—
—
—
—
—
—
Reserved for production test.
Disable PLL; CLK = CKI.
Enable PLL; CLK = 2
×
CKI (25 MHz
≤
CKI
≤
50 MHz).
Enable PLL; CLK = 5
×
CKI (10 MHz
≤
CKI
≤
20 MHz).
Enable PLL; CLK = 10
×
CKI (5 MHz
≤
CKI
≤
10 MHz).
Execute from EROM (branch to location 0x80000).
0x0111
0x0222
0x0444
0x0FFF
—
Execute from DPRAM (branch to location 0x00000).
Command
Code
mwait
Setting
Function/Download
Download
From
Download
To
Configuration
PHIF16
Mode
MIOU0
DMA
Block
External
Bus
Logical
Transfer
PODS/
PDS
Byte-
Swapping
The boot routine configures the PHIF16 by writing to the
PHIFC
register. Specifically, the external bus configuration, logical transfer size, and
byte swapping are controlled by the PMODE and PCFIG fields, the mode is controlled by the PSTROBE field, and the PODS/PDS active-
low/high configuration is controlled by the PSTRB field. After the download is complete, the boot routine returns the PHIF16 to its initial state
(configures it for Intelmode with an 8-bit external bus and 8-bit logical transfers).
This is the size of each input DMA transfer that the boot routine directs the MIOU0 to perform without core intervention. MIOU0 performs
input DMA from the PHIF16 block. The boot routine configures the input block size by programming the
ILEN0
register.
§ The first 60 Kword locations of the segment are copied into the DPRAM.