參數(shù)資料
型號: DSP16210
英文描述: TVS 400W 6.5V UNIDIRECT SMA
中文描述: DSP16210數(shù)字信號處理器
文件頁數(shù): 139/173頁
文件大小: 2621K
代理商: DSP16210
Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
139
Timing Characteristics and Requirements
(continued)
Phase-Lock Loop
Table 87. Frequency Ranges for PLL Output
Parameter
PLL Output
Frequency Range
(V
DD
= 3.3 V
±
0.3 V)
Input Jitter at CKI
Table 88. PLL Loop Filter Settings and Lock-In Time
Symbol
f
PLL
Min
50
Max
120
Unit
MHz
The values of M and N in the
pllc
register (see
Table 64 on page 105
) must be set so that f
PLL
is in the
appropriate range. Choose the lowest value of N and then the appropriate value of M for
f
CLK
= f
PLL
= f
CKI
×
M/2N.
200
ps-rms
M
pllc[11:8] (LF[3:0])
1011
1010
1001
1000
0111
0110
0100
Typical Lock-In Time (μs)
30
30
30
30
30
30
30
Lock-in time is the time following assertion of the PLLEN bit of the
pllc
register
during which the PLL output clock is unstable. The DSP must operate from the
CKI input clock or from the slow ring oscillator while the PLL is locking. The
DSP16210 signals completion of the lock-in interval by setting the LOCK flag.
23—24
21—22
19—20
16—18
12—15
8—11
2—7
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