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參數(shù)資料
| 型號： | DSP16210 |
| 英文描述： | TVS 400W 6.5V UNIDIRECT SMA |
| 中文描述： | DSP16210數(shù)字信號處理器 |
| 文件頁數(shù)： | 9/173頁 |
| 文件大小： | 2621K |
| 代理商： | DSP16210 |
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Data Sheet
July 2000
DSP16210 Digital Signal Processor
Lucent Technologies Inc.
DRAFT COPY
9
Notation Conventions
The following notation conventions apply to this data
sheet:
lower-case
Registers that are directly writable or
readable by DSP16210 core instruc-
tions are lower-case.
UPPER-CASE Device flags, I/O pins, and registers
that are not directly writable or read-
able by DSP16210 core instructions
are upper-case.
boldface
Register names and DSP16210 core
instructions are printed in boldface
when used in text descriptions.
italics
Documentation variables that are re-
placed are printed in italics.
DSP16210 program examples are
printed in courier font.
[ ]
Square brackets enclose a range of
numbers that represents multiple bits in
a single register or bus. The range of
numbers is delimited by a colon. For
example,
ioc
[7:5] are bits 7—5 of the
program-accessible
ioc
register.
Angle brackets enclose a list of items
delimited by commas or a range of
items delimited by a dash (—), one of
which is selected if used in an
instruction. For example,
ICSB
0—7
represents the eight memory-mapped
registers
ICSB0
,
ICSB1
, . . . ,
ICSB7
,
and the general instruction
aTE
h,l
= RB
can be replaced with
a0h = timer0
.
courier
Hardware Architecture
The DSP16210 device is a 16-bit fixed-point program-
mable digital signal processor (DSP). The DSP16210
consists of a DSP16000 core together with on-chip
memory and peripherals. Advanced architectural fea-
tures with an expanded instruction set deliver a dra-
matic increase in performance for signal coding
algorithms. This increase in performance together with
an efficient design implementation results in an
extremely cost- and power-efficient solution for wireless
and multimedia applications.
DSP16210 Architectural Overview
Figure 1 on page 10
shows a block diagram of the
DSP16210. The following blocks make up this device.
DSP16000 Core
The DSP16000 core is the signal-processing engine of
the DSP16210. It is a modified Harvard architecture
with separate sets of buses for the instruction/coeffi-
cient (X-memory) and data (Y-memory) spaces. Each
set of buses has 20 bits of address and 32 bits of data.
The core contains data and address arithmetic units
and control for on-chip memory and peripherals.
Clock Synthesizer (PLL)
The DSP16210 exits device reset with an input clock
(CKI) as the source for the internal clock (CLK). An on-
chip clock synthesizer (PLL) that runs at a frequency
multiple of CKI can also be used to generate CLK. The
clock synthesizer is deselected and powered down on
reset. For low-power operation, an internally generated
slow clock can drive the DSP
The clock synthesizer and other programmable clock
sources are discussed in
Clock Synthesis beginning on
page 56
. The use of these programmable clock
sources for power management is discussed in
Power
Management beginning on page 61
.
Dual-Port RAM (DPRAM)
This block contains 60 banks (banks 1—60) of zero
wait-state memory. Each bank consists of 1K 16-bit
words and has separate address and data ports to the
instruction/coefficient (X-memory) and data (Y-mem-
ory) spaces. DPRAM is organized into even and odd
interleaved banks where each even/odd pair is a 32-bit
wide module (see
Figure 4 on page 25
for details).
Placing instructions and Y-memory data in the same 2K
module of DPRAM is not supported and may cause
undefined results.
A program can be downloaded from slow off-chip mem-
ory into DPRAM, and then executed without wait-
states. DPRAM is also useful for improving convolution
performance in cases where the coefficients are adap-
tive. Since DPRAM can be downloaded through the
JTAG port, full-speed remote in-circuit emulation is
possible.
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