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MPC603e & EC603e RISC Microprocessors User's Manual
MOTOROLA
The bits in the IABR are defined as shown in Table 2-7.
2.1.2.7 Run_N Counter Register (Run_N)
The 33-bit Run_N counter register is unique to the PID7v-603e. The Run_N counter is used
by the COP to control the number of processor cycles that the processor runs before halting.
The most-significant 32 bits form a 32-bit counter. The function of the least-significant bit
remains unchanged.
2.2 Operand Conventions
This section describes the operand conventions as they are represented in two levels of the
PowerPC architecture. It also provides detailed descriptions of conventions used for storing
values in registers and memory, accessing the 603e’s registers, and representation of data
in these registers.
2.2.1 Floating-Point Execution Models—UISA
Note that the floating-point execution models are not supported on the EC603e
microprocessor.
The IEEE 754 standard includes 64- and 32-bit arithmetic. The standard requires that
single-precision arithmetic be provided for single-precision operands. The standard permits
double-precision arithmetic instructions to have either (or both) single-precision or double-
precision operands, but states that single-precision arithmetic instructions should not accept
double-precision operands.
The PowerPC UISA follows these guidelines:
Double-precision arithmetic instructions may have single-precision operands but
always produce double-precision results.
Single-precision arithmetic instructions require all operands to be single-precision
and always produce single-precision results.
For arithmetic instructions, conversions from double- to single-precision must be done
explicitly by software, while conversions from single- to double-precision are done
implicitly.
All PowerPC implementations provide the equivalent of the following execution models to
ensure that identical results are obtained. The definition of the arithmetic instructions for
Table 2-7. Instruction Address Breakpoint Register Bit Settings
Bit
Description
0–29
Word address to be compared
30
IABR enabled. Setting this bit indicates that the IABR exception is enabled.
31
Reserved