
MOTOROLA
Chapter 1. Overview
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1.1.2 System Design and Programming Considerations
The 603e is built upon the low power dissipation, low cost and high performance attributes
of the 603 while providing the system designer additional capabilities through higher
processor clock speeds (to 100 MHz), increases in cache size (16-Kbyte instruction and
data caches) and set associativity (four-way), and greater system clock flexibility. The
following subsections describe the differences between the 603 and the 603e that affect the
system designer and programmer already familiar with the operation of the 603.
The design enhancements to the 603e are described in the following sections as changes
that can require a modification to the hardware or software configuration of a system
designed for the 603.
1.1.2.1 Hardware Features
The following hardware features of the 603e may require system designers to modify
systems designed for the 603.
1.1.2.1.1 Replacement of XATS Signal by CSE1 Signal
The 603e employs four-way set associativity for both the instruction and data caches, in
place of the two-way set associativity used in the 603. This change requires the use of an
additional cache set entry (CSE1) signal to indicate which member of the cache set is being
loaded during a cache line fill. The CSE1 signal on the 603e is in the same pin location as
the XATS signal on the 603. Note that the XATS signal is no longer needed by the 603e
because support for access to direct-store segments has been removed.
Table 1-1 shows the CSE[0–1] signal encoding indicating the cache set element selected
during a cache load operation.
1.1.2.1.2 Addition of Half-Clock Bus Multipliers
Some of the reserved clock configuration signal settings of the 603 are redefined to allow
more flexible selection of higher internal and bus clock frequencies. The 603e provides
programmable internal processor clock rates of 1x, 1.5x, 2x, 2.5x, 3x, 3.5x, and 4x
multiples of the externally supplied clock frequency. For additional information, refer to the
appropriate device-specific hardware specifications.
Table 1-1. CSE[0–1] Signals
CSE[0–1]
Cache Set Element
00
Set 0
01
Set 1
10
Set 2
11
Set 3