
1-14
MPC603e & EC603e RISC Microprocessors User's Manual
MOTOROLA
snoop is retried and must re-arbitrate for access to the cache. Loads or stores that are
deferred due to snoop accesses are executed on the clock cycle following the snoop.
1.1.6 Processor Bus Interface
Because the caches on the 603e are on-chip, write-back caches, the predominant type of
transaction for most applications is burst-read memory operations, followed by burst-write
memory operations, and single-beat (noncacheable or write-through) memory read and
write operations. Additionally, there can be address-only operations, variants of the burst
and single-beat operations, (for example, global memory operations that are snooped and
atomic memory operations), and address retry activity (for example, when a snooped read
access hits a modified line in the cache).
Memory accesses can occur in single-beat (1–8 bytes) and four-beat burst (32 bytes) data
transfers when the bus is configured as 64 bits, and in single-beat (1–4 bytes), two-beat (8
bytes), and eight-beat (32 bytes) data transfers when the bus is configured as 32 bits. The
address and data buses operate independently to support pipelining and split transactions
during memory accesses. The 603e can pipeline its own transactions to a depth of one level.
Access to the system interface is granted through an external arbitration mechanism that
allows devices to compete for bus mastership. This arbitration mechanism is flexible,
allowing the 603e to be integrated into systems that implement various fairness and bus
parking procedures to avoid arbitration overhead.
Typically, memory accesses are weakly ordered—sequences of operations, including
load/store string and multiple instructions, do not necessarily complete in the order they
begin—maximizing the efficiency of the bus without sacrificing coherency of the data. The
603e allows read operations to precede store operations (except when a dependency exists,
or in cases where a non-cacheable access is performed), and provides support for a write
operation to proceed a previously queued read data tenure (for example, allowing a snoop
push to be enveloped by the address and data tenures of a read operation). Because the
processor can dynamically optimize run-time ordering of load/store traffic, overall
performance is improved.
1.1.7 System Support Functions
The 603e implements several support functions that include power management, time
base/decrementer registers for system timing tasks, an IEEE 1149.1(JTAG)/common
on-chip processor (COP) test interface, and a phase-locked loop (PLL) clock multiplier.
These system support functions are described in the following subsections.