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MPC603e & EC603e RISC Microprocessors User's Manual
MOTOROLA
The instruction pipeline in the 603e has four major pipeline stages, described as follows:
The fetch pipeline stage primarily involves retrieving instructions from the memory
system and determining the location of the next instruction fetch. Additionally, the
BPU decodes branches during the fetch stage and folds out branch instructions
before the dispatch stage if possible.
The dispatch pipeline stage is responsible for decoding the instructions supplied by
the instruction fetch stage, and determining which of the instructions are eligible to
be dispatched in the current cycle. In addition, the source operands of the
instructions are read from the appropriate register file and dispatched with the
instruction to the execute pipeline stage. At the end of the dispatch pipeline stage,
the dispatched instructions and their operands are latched by the appropriate
execution unit.
During the execute pipeline stage each execution unit that has an executable
instruction executes the selected instruction (perhaps over multiple cycles), writes
the instruction's result into the appropriate rename register, and notifies the
completion stage that the instruction has finished execution. In the case of an internal
exception, the execution unit reports the exception to the completion/writeback
pipeline stage and discontinues instruction execution until the exception is handled.
The exception is not signaled until that instruction is the next to be completed.
Execution of most floating-point instructions is pipelined within the FPU allowing
up to three instructions to be executing in the FPU concurrently. The pipeline stages
for the floating-point unit are multiply, add, and round-convert. Execution of most
load/store instructions is also pipelined. The load/store unit has two pipeline stages.
The first stage is for effective address calculation and MMU translation and the
second stage is for accessing the data in the cache. (Note that the EC603e
microprocessor does not support the floating-point unit.)
The complete/writeback pipeline stage maintains the correct architectural machine
state and transfers the contents of the rename registers to the GPRs and FPRs as
instructions are retired. If the completion logic detects an instruction causing an
exception, all following instructions are cancelled, their execution results in rename
registers are discarded, and instructions are fetched from the correct instruction
stream.
A superscalar processor is one that issues multiple independent instructions into multiple
pipelines allowing instructions to execute in parallel. The 603e has five independent
execution units, one each for integer instructions, floating-point instructions (floating-point
instructions are trapped by the floating-point unavailable exception on the EC603e
microprocessor), branch instructions, load/store instructions, and system register
instructions. The IU and the FPU each have dedicated register files for maintaining
operands (GPRs and FPRs, respectively), allowing integer calculations and floating-point
calculations to occur simultaneously without interference. Integer division performance of
the PID7v-603e has been improved, with the
divwu
x
and
divw
x
instructions executing in
20 clock cycles, instead of the 37 cycles required in the PID6-603e.