
5-4
MPC603e & EC603e RISC Microprocessors User's Manual
MOTOROLA
Figure 5-2 and Figure 5-3 show the conceptual organization of the 603e instruction and
data MMUs, respectively. The instruction addresses shown in Figure 5-2 are generated by
the processor for sequential instruction fetches and addresses that correspond to a change
of program flow. Data addresses shown in Figure 5-3 are generated by load and store
instructions and by cache instructions.
As shown in the figures, after an address is generated, the higher-order bits of the effective
address, EA0–EA19 (or a smaller set of address bits, EA0–EA
n
, in the cases of blocks), are
translated into physical address bits PA0–PA19. The lower-order address bits, A20–A31 are
untranslated and therefore identical for both effective and physical addresses. After
translating the address, the MMUs pass the resulting 32-bit physical address to the memory
subsystem.
In addition to the higher-order address bits, the MMUs automatically keep an indicator of
whether each access was generated as an instruction or data access and a supervisor/user
indicator that reflects the state of the PR bit of the MSR when the effective address was
generated. In addition, for data accesses, there is an indicator of whether the access is for a
load or a store operation. This information is then used by the MMUs to appropriately direct
the address translation and to enforce the protection hierarchy programmed by the
operating system. Section 4.2, “Exception Processing,” describes the MSR, which controls
some of the critical functionality of the MMUs.
The figures show the way in which the A20–A26 address bits index into the on-chip
instruction and data caches to select a cache set. The remaining physical address bits are
then compared with the tag fields (comprised of bits PA0–PA19) of the four selected cache
blocks to determine if a cache hit has occurred. In the case of a cache miss, the instruction
or data access is then forwarded to the bus interface unit which then initiates an external
memory access.