
4-16
MPC603e & EC603e RISC Microprocessors User's Manual
MOTOROLA
4.2.4 Returning from an Exception Handler
The Return from Interrupt (
rfi
) instruction performs context synchronization by allowing
previously issued instructions to complete before returning to the interrupted process. In
general, execution of the
rfi
instruction ensures the following:
All previous instructions have completed to a point where they can no longer cause
an exception. If a previous instruction causes a direct-store interface error exception,
the results must be determined before this instruction is executed.
Previous instructions complete execution in the context (privilege, protection, and
address translation) under which they were issued.
The
rfi
instruction copies SRR1 bits back into the MSR.
The instructions following this instruction execute in the context established by this
instruction.
For a complete description of context synchronization, refer to Chapter 6, “Exceptions,” of
The
Programming Environments Manual.
4.3 Process Switching
The operating system should execute one of the following when processes are switched:
The
sync
instruction, which orders the effects of instruction execution. All
instructions previously initiated appear to have completed before the
sync
instruction completes, and no subsequent instructions appear to be initiated until the
sync
instruction completes. For an example showing use of the
sync
instruction, see
Chapter 2, “PowerPC Register Set,” of
The
Programming Environments Manual.
The
isync
instruction, which waits for all previous instructions to complete and then
discards any fetched instructions, causing subsequent instructions to be fetched (or
refetched) from memory and to execute in the context (privilege, translation,
protection, etc.) established by the previous instructions.
The
stwcx.
instruction, to clear any outstanding reservations, which ensures that an
lwarx
instruction in the old process is not paired with an
stwcx.
instruction in the
new process.
The operating system should set the MSR[RI] bit as described in Section 4.2.3, “Setting
MSR[RI].”