
MOTOROLA
Chapter 1. Overview
1-27
the PID7v-603e, the critical double word is simultaneously written to the cache and
forwarded to the requesting unit, thus minimizing stalls due to load delays.
To ensure coherency among caches in a multiprocessor (or multiple caching-device)
implementation, the 603e implements the MEI protocol. These three states, modified,
exclusive, and invalid, indicate the state of the cache block as follows:
Modified—The cache block is modified with respect to system memory; that is, data
for this address is valid only in the cache and not in system memory.
Exclusive—This cache block holds valid data that is identical to the data at this
address in system memory. No other cache has this data.
Invalid—This cache block does not hold valid data.
Cache coherency is enforced by on-chip bus snooping logic. Since the 603e’s data cache
tags are single-ported, a simultaneous load or store and snoop access represent a resource
contention. The snoop access is given first access to the tags. The load or store then occurs
on the clock following the snoop.
Figure 1-3. Data Cache Organization
1.3.4 Exception Model
This section describes the PowerPC exception model and the 603e implementation,
specifically. PID7v-603e–specific information is noted where applicable.
1.3.4.1 PowerPC Exception Model
The PowerPC exception mechanism allows the processor to change to supervisor state as a
result of external signals, errors, or unusual conditions arising in the execution of
instructions, and differ from the arithmetic exceptions defined by the IEEE for
floating-point operations. When exceptions occur, information about the state of the
processor is saved to certain registers and the processor begins execution at an address
Address Tag 1
Address Tag 2
Address Tag 3
Block 1
Block 2
Block 3
128 Sets
Address Tag 0
Block 0
8 Words/Block
State
State
State
Words 0–7
Words 0–7
Words 0–7
Words 0–7
State