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MPC603e & EC603e RISC Microprocessors User's Manual
MOTOROLA
Instruction dispatch/execution—(Program, DSI, alignment, emulation trap, system
call, DTLB miss on load or store, IABR). This type of exception is determined at
dispatch or execution of an instruction. The exception remains pending until all
instructions in program order before the exception-causing instruction are
completed. The exception is then taken without completing the exception-causing
instruction. If any other exception condition is created in completing these previous
instructions in the machine, that exception takes priority over the pending
instruction dispatch/execution exception, which will then be forgotten.
Post–instruction execution—(Trace). This type of exception is generated following
execution and completion of an instruction while a trace mode is enabled. If
executing the instruction produces conditions for another type of interrupt, that
exception is taken and the post-instruction execution exception is forgotten for that
instruction.
4.2 Exception Processing
When an exception is taken, the processor uses the save/restore registers, SRR0 and SRR1,
to save the contents of the machine state register for user-level mode (referred to as problem
mode in the architecture specification) and to identify where instruction execution should
resume after the exception is handled.
When an exception occurs, SRR0 is set to point to the instruction at which instruction
processing should resume when the exception handler returns control to the interrupted
process. All instructions in the program flow preceding this one will have completed and
no subsequent instruction will have completed. This may be the address of the instruction
that caused the exception or the next one (as in the case of a system call exception). The
instruction addressed can be determined from the exception type and status bits. This
address is used to resume instruction processing in the interrupted process, typically when
an
rfi
instruction is executed. The SRR0 register is shown in Figure 4-2
.
Figure 4-2. Machine Status Save/Restore Register 0
The save/restore register 1 (SRR1) is used to save machine status (the contents of the MSR)
on exceptions and to restore those values when
rfi
is executed. SRR1 is shown in
Figure 4-3.
Figure 4-3. Machine Status Save/Restore Register 1
SRR0 (holds EA for resuming program execution)
0
31
0
31
Exception-specific information and MSR bit values