
MOTOROLA
Contents
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CONTENTS
Paragraph
Number
Title
Page
Number
Chapter 2
Programming Model
2.1
2.1.1
2.1.2
2.1.2.1
2.1.2.2
Register Set ..........................................................................................................2-1
PowerPC Register Set......................................................................................2-1
Implementation-Specific Registers..................................................................2-7
Hardware Implementation Registers (HID0 and HID1)..............................2-7
Data and Instruction TLB Miss Address Registers
(DMISS and IMISS)................................................................................2-9
Data and Instruction TLB Compare Registers
(DCMP and ICMP)..................................................................................2-9
Primary and Secondary Hash Address Registers
(HASH1 and HASH2) ...........................................................................2-10
Required Physical Address Register (RPA)...............................................2-11
Instruction Address Breakpoint Register (IABR)......................................2-11
Run_N Counter Register (Run_N).............................................................2-12
Operand Conventions.........................................................................................2-12
Floating-Point Execution Models—UISA.....................................................2-12
Data Organization in Memory and Data Transfers........................................2-13
Alignment and Misaligned Accesses.............................................................2-13
Floating-Point Operand..................................................................................2-14
Effect of Operand Placement on Performance...............................................2-14
Instruction Set Summary....................................................................................2-15
Classes of Instructions....................................................................................2-16
Definition of Boundedly Undefined ..........................................................2-16
Defined Instruction Class...........................................................................2-16
Illegal Instruction Class .............................................................................2-17
Reserved Instruction Class.........................................................................2-18
Addressing Modes..........................................................................................2-18
Memory Addressing...................................................................................2-18
Memory Operands......................................................................................2-18
Effective Address Calculation ...................................................................2-19
Synchronization .........................................................................................2-19
Context Synchronization........................................................................2-20
Execution Synchronization....................................................................2-20
Instruction-Related Exceptions..............................................................2-20
Instruction Set Overview................................................................................2-21
PowerPC UISA Instructions ..........................................................................2-21
Integer Instructions ....................................................................................2-21
Integer Arithmetic Instructions..............................................................2-22
Integer Compare Instructions.................................................................2-22
Integer Logical Instructions...................................................................2-23
Integer Rotate and Shift Instructions .....................................................2-24
2.1.2.3
2.1.2.4
2.1.2.5
2.1.2.6
2.1.2.7
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.3
2.3.1
2.3.1.1
2.3.1.2
2.3.1.3
2.3.1.4
2.3.2
2.3.2.1
2.3.2.2
2.3.2.3
2.3.2.4
2.3.2.4.1
2.3.2.4.2
2.3.2.4.3
2.3.3
2.3.4
2.3.4.1
2.3.4.1.1
2.3.4.1.2
2.3.4.1.3
2.3.4.1.4