
MOTOROLA
Contents
iii
CONTENTS
Paragraph
Number
Title
Page
Number
About This Book
Audience............................................................................................................ xxix
Organization....................................................................................................... xxix
Suggested Reading...............................................................................................xxx
Conventions.....................................................................................................xxxiii
Acronyms and Abbreviations .......................................................................... xxxiv
Terminology Conventions ..............................................................................xxxvii
Chapter 1
Overview
1.1
1.1.1
1.1.2
1.1.2.1
1.1.2.1.1
1.1.2.1.2
1.1.2.2
1.1.2.2.1
1.1.2.2.2
1.1.2.2.3
1.1.3
1.1.3.1
1.1.3.2
1.1.4
1.1.4.1
1.1.4.2
1.1.4.3
1.1.4.4
1.1.4.5
1.1.5
1.1.5.1
1.1.5.2
1.1.6
Overview..............................................................................................................1-1
Features............................................................................................................1-2
System Design and Programming Considerations...........................................1-7
Hardware Features.......................................................................................1-7
Replacement of
XATS
Signal by CSE1 Signal.......................................1-7
Addition of Half-Clock Bus Multipliers..................................................1-7
Software Features ........................................................................................1-8
16-Kbyte Instruction and Data Caches....................................................1-8
Clock Configuration Available in HID1 Register...................................1-8
Performance Enhancements.....................................................................1-8
Instruction Unit................................................................................................1-9
Instruction Queue and Dispatch Unit ..........................................................1-9
Branch Processing Unit (BPU)....................................................................1-9
Independent Execution Units.........................................................................1-10
Integer Unit (IU)........................................................................................1-10
Floating-Point Unit (FPU).........................................................................1-10
Load/Store Unit (LSU)..............................................................................1-11
System Register Unit (SRU)......................................................................1-11
Completion Unit ........................................................................................1-11
Memory Subsystem Support..........................................................................1-12
Memory Management Units (MMUs).......................................................1-12
Cache Units................................................................................................1-13
Processor Bus Interface .................................................................................1-14