
MOTOROLA
Chapter 4. Exceptions
4-29
Note that the PowerPC architecture allows individual processors to determine whether an
exception is required to handle various alignment conditions. The 603e initiates an
alignment exception when it detects any of the following conditions:
The operand of a floating-point load or store operation is not word-aligned.
The operand of a
dcbz
instruction is in a page that is write-through or caching-
inhibited for a virtual mode access.
The operand of an
lmw
,
stmw
,
lwarx
, or
stwcx
. instruction is not word-aligned.
Note that unlike other alignment exceptions, which store the address as computed
by the instruction in the DAR, alignment exceptions for load or store multiple
instructions store that address value + 4 into the DAR.
A little-endian access is misaligned.
A multiple access is attempted while the little-endian, MSR[LE], bit is set.
4.5.7 Program Exception (0x00700)
The 603e implements the program exception as it is defined by the PowerPC architecture
(OEA). A program exception occurs when no higher priority exception exists and one or
more of the exception conditions defined in the OEA occur.
When a program exception is taken, instruction execution for the handler begins at offset
0x00700 from the physical base address indicated by MSR[IP]. The exception conditions
are as follows:
Floating-point enabled exception—These exceptions correspond to IEEE-defined
exception conditions, such as overflows, and divide by zeros that may occur during
the execution of a floating-point arithmetic instruction. As a group, these exceptions
are enabled by the FE0 and FE1 bits in the in the MSR. Individual conditions are
enabled by specific bits in the FPSCR. For general information about this exception,
see
The
Programming Environments Manual
. For more information about how these
exceptions are implemented in the 603e, see Section 4.5.7.1, “IEEE Floating-Point
Exception Program Exceptions.”
Note:
The floating-point enabled exception is not supported on the EC603e
microprocessor.
Illegal instruction—An illegal instruction program exception is generated when
execution of an instruction is attempted with an illegal opcode or illegal combination
of opcode and extended opcode fields (including PowerPC instructions not
implemented in the 603e). These do not include those optional instructions treated
as no-ops.
Privileged instruction—A privileged instruction type program exception is
generated when the execution of a privileged instruction is attempted and the MSR
register user privilege bit, MSR[PR], is set. In the 603e, this exception is generated
for
mtspr
or
mfspr
with an invalid SPR field if SPR[0] = 1 and MSR[PR] = 1. This
may not be true for all PowerPC processors.