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MPC603e & EC603e RISC Microprocessors User's Manual
MOTOROLA
If the prediction is incorrect, the fetched instructions are purged, and instruction fetching
continues along the alternate path. See Chapter 8, “Instruction Timing,” in
The
Programming Environments Manual
for more information about how branches are
executed.
2.3.4.4.1 Branch Instruction Address Calculation
Branch instructions can alter the sequence of instruction execution. Instruction addresses
are always assumed to be word aligned; the processor ignores the two low-order bits of the
generated branch target address.
Branch instructions compute the effective address (EA) of the next instruction address
using the following addressing modes:
Branch relative
Branch conditional to relative address
Branch to absolute address
Branch conditional to absolute address
Branch conditional to link register
Branch conditional to count register
2.3.4.4.2 Branch Instructions
Table 2-27 lists the branch instructions provided by the PowerPC processors. To simplify
assembly language programming, a set of simplified mnemonics and symbols is provided
for the most frequently used forms of branch conditional, compare, trap, rotate and shift,
and certain other instructions. See Appendix F, “Simplified Mnemonics,” in
The
Programming Environments Manual
for a list of simplified mnemonic examples.
2.3.4.4.3 Condition Register Logical Instructions
Condition register logical instructions, shown in Table 2-28, and the Move Condition
Register Field (
mcrf
) instruction are also defined as flow control instructions, although they
are executed by the system register unit (SRU). Most instructions executed by the SRU are
Table 2-27. Branch Instructions
Name
Mnemonic
Operand Syntax
Branch
b (ba
bl bla)
target_addr
Branch Conditional
bc (bca
bcl bcla)
BO
,
BI
,
target_addr
Branch Conditional to Link Register
bclr (bclrl)
BO
,
BI
Branch Conditional to Count Register
bcctr (bcctrl)
BO
,
BI