
MOTOROLA
Chapter 3. Instruction and Data Cache Operation
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Chapter 3
Instruction and Data Cache Operation
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The PowerPC 603e microprocessor provides two 16-Kbyte, four-way set associative caches
to allow the registers and execution units rapid access to instructions and data. Both the
instruction and data caches are tightly coupled to the 603e’s bus interface unit (BIU) to
allow efficient access to the system memory controller and other bus masters. The 603e’s
load/store unit (LSU) is also directly coupled to the data cache to allow the efficient
movement of data to and from the general-purpose and floating-point registers. (The
floating-point register file is not supported on the EC603e microprocessor.)
Both the instruction and data caches have a block size of 32 bytes, and the data cache blocks
can be snooped, or cast-out when the cache block is reloaded. The data cache is designed
to adhere to a write-back policy, but the 603e allows control of cacheability, write-back
policy, and memory coherency at the page and block level. Both caches use a least recently
used (LRU) replacement policy. Burst fill operations to the caches result from cache misses,
or in the case of the data cache, cache block write-back operations to memory. Note that in
the PowerPC architecture, the term ‘cache block’, or simply ‘block’ when used in the
context of cache implementations, refers to the unit of memory at which coherency is
maintained. For the 603e, the block size is equivalent to the eight-word cache line. This
value may be different for other PowerPC implementations.
The data cache is configured as 128 sets of four blocks. Each block consists of 32 bytes,
two state bits, and an address tag. The two state bits implement the three-state MEI
(modified/exclusive/invalid) protocol, a coherent subset of the standard four-state MESI
protocol. Cache coherency is enforced by on-chip bus snooping logic. Since the 603e’s data
cache tags are single-ported, a simultaneous load or store and snoop access represent a
resource contention. The snoop access is given first access to the tags. Load or store
operations can be performed to the cache on the clock cycle immediately following a snoop
access if the snoop misses; snoop hits may block the data cache for two or more cycles,
depending on whether a copyback to main memory is required.
The instruction cache also consists of 128 sets of four blocks, and each block consists of 32
bytes, an address tag, and a valid bit. The instruction cache is only written as a result of a
block fill operation on a cache miss. In the PID7v-603e, the instruction cache is blocked
only until the critical load completes. The PID7v-603e supports instruction fetching from
other instruction cache lines following the forwarding of the critical first double word of a
cache line load operation. Successive instruction fetches from the cache line being loaded