
4-8
Configuration Registers
4.1.3.11
To Set Up the General-Purpose and PMC Pins
4.1.3.12
To Control the Clocks (Phase-Locked Loops)
See
And program bits
“Miscellaneous 6 Register (Index 70h)” on page 4-35
6
“MMSB Control Register (Index 74h)” on page 4-39
2
“Power Control 1 Register (Index 80h)” on page 4-42
6 and 2
“Power Control 2 Register (Index 81h)” on page 4-43
6 and 2
“General-Purpose I/O 0 Register (Index 89h)” on page 4-46
7–0
“General-Purpose I/O Control Register (Index 91h)” on page 4-47
7–0
“General-Purpose I/O 2 Register (Index 94h)” on page 4-49
7–0
“General-Purpose I/O 3 Register (Index 95h)” on page 4-49
7–0
“General-Purpose I/O 1 Register (Index 9Ch)” on page 4-51
7–0
“CPU Status 0 Register (Index A3h)” on page 4-54
0
“CPU Status 1 Register (Index A4h)” on page 4-55
3
“Power Control 3 Register (Index ABh)” on page 4-58
7–0
“Power Control 4 Register (Index ACh)” on page 4-59
7–0
“PMU Control 3 Register (Index ADh)” on page 4-60
3
“PIRQ Configuration Register (Index B2h)” on page 4-64
7–4 and 3–0
“Miscellaneous 3 Register (Index BAh)” on page 4-70
4–3
See
And program bits
“I/O Wait State Register (Index 61h)” on page 4-22
6
“Miscellaneous 2 Register (Index 6Bh)” on page 4-30
2
“MMSB Control Register (Index 74h)” on page 4-39
3
“Control B Register (Index 77h)” on page 4-42
3
“Power Control 1 Register (Index 80h)” on page 4-42
7
“Power Control 2 Register (Index 81h)” on page 4-43
7 and 3
“Clock Control Register (Index 8Fh)” on page 4-47
2–0
“UART Clock Enable Register (Index 92h)” on page 4-49
0
“Auto Low-Speed Control Register (Index 9Fh)” on page 4-51
3–0
“PMU Control 3 Register (Index ADh)” on page 4-60
3–0
“PMU Control 2 Register (Index AFh)” on page 4-61
5 and 0
“Function Enable 1 Register (Index B0h)” on page 4-61
6 and 3
“Function Enable 2 Register (Index B1h)” on page 4-62
4–2
“Miscellaneous 3 Register (Index BAh)” on page 4-70
3