
1-28
Power Management
1.7.3
Processing NMI or SMI Source
On reset, firmware must check bit 7 of the Version register at Index 64h to determine if
the reset was caused by an SMI. Upon receiving an SMI and entering the SMI handler,
the CPU must then poll the various SMI status registers to determine the source of the
SMI. The status registers are as follows:
I
Miscellaneous 5 register at Index B3h for the EXTSMI pin
I
SMI Status register at Index 43h for the following sources:
— Hard disk drive
— Floppy disk drive
— Programmable I/O
— 8042 accesses
— RTC accesses
— IRQ0 generation
— PMU status changes
If PMU status changes (bit 5) cause the SMI, the SMI handler must read the NMI/SMI
Control register at Index A5h to determine the source of the PMU SMI.
If the SMI or NMI is caused by either PMU status changes or IRQ0 generation, the PMU
Status 1 register at Index A2h must be written in order to reset the SMI generation logic.
This write must occur after reading the SMI Status register at Index 43h and the NMI/SMI
Control register at Index A5h. Failure to follow this order may result in additional SMIs
being generated with incorrect status.
If the SMI or NMI was caused by a PMU status change, a write to the NMI/SMI Control
register must occur near the end of the routine. Prior to performing this write, the
NMI/SMI Control register should be read again to determine if additional PMU status
changes need to be processed. If additional PMU status changes need to be processed,
the write to the NMI/SMI Control register should be delayed, the PMU Status 1 register
should again be written, and any code specific to the new status change should be exe-
cuted.
A condition exists where the SMI or NMI state-transition status (as reflected in the
NMI/SMI Control register at Index A5h) can be different than the PMU’s current state. If a
state-transition SMI or NMI is received (and subsequently queued by the PMU logic)
while the system is executing another state-transition SMI or NMI routine, and the system
is forced to another state via the Software Mode Control register at Index 88h, beforeexit-
ing the routine but afterclearing the NMI/SMI Control register (to allow the state transi-
tion), then an incoherency causing the difference can occur.
The source of the incoherency lies in the fact that as soon as the current SMI or NMI
completes, the CPU begins processing the queued-up state-transition SMI or NMI. Upon
entry to the handler, if the code reads the NMI/SMI Control register to determine the
source of the SMI/NMI, the PMU reports a state transition based on the mode change
beforethe write to the Software Mode Control register, while a read of the current state as
shown in the CPU Status 1 register at Index A4h reports the mode that occurred afterthe
write to the Software Mode Control register.