
I-18
INDEX
ROM Configuration 3 Register (Index B8h)
accessing ROM-DOS address space,
2-8
bit descriptions,
4-67
controlling number of wait states,
2-16
enabling high-speed clock rate,
2-16
ROM DOS enable and wait-state logic (table),
4-67
ROM DOS linear address decode size select logic
(table),
4-68
ROM DOS memory,
2-8
command delay select logic (table),
4-19
description,
2-8
enable and wait-state logic (table),
4-67
linear address decode size select logic (table),
4-68
registers for mapping and controlling (table),
4-10
wait state select logic (table),
4-19
ROM shadowing,
2-6
ROMCS signal
enabling and disabling,
2-6
–
2-7
high-speed clock ROM cycles,
2-15
ROM chip-select command gating,
2-14
ROM chip-select signal,
2-15
wait-state control-bit logic (table),
2-16
ROMDOS16 bit,
4-20
ROMWS0 bit,
4-20
ROMWS1 bit,
4-20
RS3–RS0 bits,
3-17
RTC Index Data Register (Port 071h),
3-21
RTC registers. Seereal-time clock.
RTCSMIEN bit
SMI Enable Register (Index 41h),
4-13
SMI I/O Status Register (Index 42h),
4-14
RTS bit,
3-14
S
SACIN bit,
4-35
SB bit,
3-13
SC03 bit,
4-29
SC2-SC0 bits,
4-50
SC47 bit,
4-29
SC8B bit,
4-29
SCCF bit,
4-29
Scratch Pad Register (Ports 2FFh & 3FFh),
3-15
SD03 bit,
4-29
SD47 bit,
4-29
SD8B bit,
4-29
SDCF bit,
4-29
SE03 bit,
4-30
SE47 bit,
4-30
SE8B bit,
4-30
SECF bit,
4-30
SET bit,
3-19
SF03 bit,
4-30
SF47 bit,
4-30
SF8B bit,
4-30
SFCF bit,
4-30
SHADOW bit,
4-27
Shadow RAM Enable 1 Register (Index 68h),
4-29
Shadow RAM Enable 2 Register (Index 69h),
4-30
SHUTD bit,
4-25
SLCT bit
Parallel Status Port (Ports 279h & 379h),
3-10
Parallel Status Port (Ports 279h, 379h, & 3BDh),
3-9
SLCTIN bit,
3-9
Sleep mode
purpose and use,
1-7
Sleep to Suspend Timer Register (Index 86h)
description,
4-44
initializing for suspend/resume operation,
1-37
state-transition timing,
1-22
slow refresh,
1-41
,
2-3
SLP bit,
4-43
SLREF bit,
4-56
SMI and NMI control. See alsoNMIs, SMIs.
1-25
–
1-31
accesses to powered-down device SMI,
1-29
device-powerdown flowchart (figure),
1-30
enabling SMIs,
1-27
registers for (table),
1-27