
INDEX
I-17
periodic-interrupt rate-selection bits (table),
3-18
time-base divider-chain bits (table),
3-18
Register B (RTC Index 0Bh),
3-19
Register C (RTC Index 0Ch),
3-19
Register D (RTC Index 0Dh),
3-19
RTC register summary (table),
3-17
Receiver Buffer Register (Ports 2F8h & 3F8h),
3-11
refresh states
8254-based DRAM refresh,
2-3
refresh cycle wait states (table),
4-21
refresh initialization example (table),
2-3
refresh interval select logic (table),
4-27
self-refresh DRAMs,
2-17
slow refresh,
1-41
,
2-3
refresh states,
2-3
–
2-4
REFSEL bit,
4-56
REFSEL0 bit
function,
4-26
refresh interval select logic (table),
4-27
REFSEL1 bit
function,
4-26
refresh interval select logic (table),
4-27
REFWS bit,
4-20
Register A (RTC Index 0Ah)
bit descriptions,
3-17
periodic-interrupt rate-selection bits (table),
3-18
time-base divider-chain bits (table),
3-18
Register B (RTC Index 0Bh),
3-19
Register C (RTC Index 0Ch),
3-19
Register D (RTC Index 0Dh),
3-19
RESCPU bit,
4-34
Reserved Register (Index 6Ah),
4-30
Reserved Register (Index 8Bh),
4-46
Reserved Register (Index 8Eh),
4-46
Reserved Register (Index 90h),
4-47
Reserved Register (Index 93h),
4-49
Reserved Register (Index 9Dh),
4-51
Reserved Register (Index AEh),
4-60
Reserved Registers (Indexes 49–4Fh),
4-18
Reserved Registers (Indexes 52–5Fh),
4-20
Reserved Registers (Indexes 78–7Fh),
4-42
Reserved Registers (Indexes 96–99h),
4-49
RESIN pin,
1-40
RESU bit,
4-43
RESUME bit,
4-56
Resume Mask Register (Index 08h)
bit descriptions,
4-11
non-CPU activity selection,
1-19
Resume Status Register (Index 09h)
activity monitoring,
1-19
bit descriptions,
4-12
RFD bit,
3-20
RI bit,
3-15
RI signal (table),
1-23
RIMSK bit,
4-11
ring-in wake-ups,
1-24
Ring-Indicate signals,
1-23
RLSD bit,
3-15
ROM BIOS memory,
2-6
–
2-7
address initialization (table),
2-6
copying ROM contents to DRAM,
2-7
illustration,
2-7
enable and wait-state select logic (table),
4-66
high memory (figure),
2-6
registers for mapping and controlling (table),
4-10
wait states (table),
4-21
ROM chip-select command gating,
2-14
ROM chip-select signal
high-speed clock ROM cycles,
2-15
purpose and use,
2-16
ROMCS wait-state control-bit logic (table),
2-16
ROM Configuration 1 Register (Index 65h)
bit descriptions,
4-27
caution when performing read-modify-write-se-
quence (note),
2-7
setting up Page-mode DRAM accesses,
2-4
ROM Configuration 2 Register (Index 51h)
bit descriptions,
4-20
controlling ROM-DOS address space,
2-8