
4-32
Configuration Registers
Bits 7–4
(pages 0–7). These windows get mapped at different system-memory address locations
as listed in Table 4-26 on page 4-33. Once the system-memory address spaces for these
windows are programmed (i.e., the base address is selected) and the page register I/O
addresses are selected, the software can program the page registers. Software must also
program the other address extension registers (MMS Address Extension 2 register at
Index 6Eh, MMSA Address Extension 1 register at Index 67h, and MMS Address
Extension 1 register at Index 6Ch) before a page in the MMSA or the MMSB is enabled.
See the ROM Configuration 1 register at Index 65h and the MMSB Control Register at
Index 74h to enable the MMSA and the MMSB. Note that the MMSB base address is
fixed at 0A0000h and is not under software control.
Provide selection of starting addresses of memory windows in MMSA
Table 4-24
MMSA/B Page Register I/O Addresses
Bit
Page Register I/O Address
3
2
1
0
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
0
0
0
0
208h
2208h
4208h
6208h
8208h
A208h
C208h
E208h
0
0
0
1
218h
2218h
4218h
6218h
8218h
A218h
C218h
E218h
0
1
0
1
258h
2258h
4258h
6258h
8258h
A258h
C258h
E258h
0
1
1
0
268h
2268h
4268h
6268h
8268h
A268h
C268h
E268h
1
0
1
0
2A8h
22A8h
42A8h
62A8h
82A8h
A2A8h
C2A8h
E2A8h
1
0
1
1
2B8h
22B8h
42B8h
62B8h
82B8h
A2B8h
C2B8h
E2B8h
1
1
1
0
2E8h
22E8h
42E8h
62E8h
82E8h
A2E8h
C2E8h
E2E8h
Table 4-25
Page Register Contents Description
Bit
Name
R/W
Function
7
PAGEEN
R/W
0 = Page disable
1 = Page enable
6
EA20
R/W
MMSA/B translate address bit A20
5
EA19
R/W
MMSA/B translate address bit A19
4
EA18
R/W
MMSA/B translate address bit A18
3
EA17
R/W
MMSA/B translate address bit A17
2
EA16
R/W
MMSA/B translate address bit A16
1
EA15
R/W
MMSA/B translate address bit A15
0
EA14
R/W
MMSA/B translate address bit A14