
INDEX
I-15
power-management control pin settings (table),
1-12
PMC
pins.
(PMC4-PMC0) pins.
See
Power-Management
Control
PMCSMI bit,
4-14
PMU clock speeds (table),
1-6
PMU Control 1 Register (Index A7h)
bit descriptions,
4-56
data-path disabling logic,
1-41
PMU operating-mode transitions,
1-8
PMU Control 2 Register (Index AFh)
bit descriptions,
4-61
enabling BL1 pin,
1-32
state-transition timer,
1-22
PMU Control 3 Register (Index ADh)
bit descriptions,
4-60
generating PMU-activity event with ACIN pin,
1-34
low-speed PLL mode CPU clock speed select (table),
4-60
PMU operating-mode transitions,
1-8
PMU mode
last PMU mode indicator bits (table),
4-54
PMU mode select logic (table),
4-45
present PMU mode indicator bits (table),
4-55
PMU operating-mode transitions,
1-8
PMU state machine
general-purpose control using PMC pins,
1-14
purpose and use,
1-2
PMU Status 1 Register (Index A2h)
4-54
PMU Timer. SeeState-Transition Timer.
PMU. SeePower Management Unit (PMU).
PMW bit
Activity Mask 2 Register (Index 76h),
4-41
Activity Status 2 Register (Index A1h),
4-53
Port 92 (Port 092h),
3-21
Port B Register (Port 061h),
3-20
Power Control 1 Register (Index 80h)
bit descriptions,
4-42
merging PMU modes,
1-9
shutting down low-speed and video PLLs in Doze
mode,
1-6
Power Control 2 Register (Index 81h)
bit descriptions,
4-43
merging PMU modes,
1-9
shutting down low-speed and video PLLs
Sleep mode,
1-7
Suspend mode,
1-7
Power Control 3 Register (Index ABh),
4-58
Power Control 4 Register (Index ACh),
4-59
Power Management Unit (PMU),
1-2
–
1-13
clock sources,
1-9
components,
1-2
–
1-3
merging PMU modes,
1-9
operating-mode transitions
description,
1-8
illustration,
1-4
power conservation techniques,
1-2
power management modes,
1-3
–
1-8
Doze mode,
1-5
–
1-6
High-Speed PLL mode,
1-4
–
1-5
Low-Speed PLL mode,
1-5
Off mode,
1-7
–
1-8
overview,
1-3
PMU clock speeds (table),
1-6
Sleep mode,
1-7
Suspend mode,
1-7
programming examples
inactivity states and transition intervals (table),
1-10
peripheral-device power,
1-11
–
1-13
PIO timeout settings (table),
1-12
power management control pin settings (table),
1-12
power-management setup,
1-9
–
1-11
table,
1-11
SMI-generation settings for PIO accesses (table),
1-13
reading PMU mode,
1-9
power management. See also Power Management Unit
(PMU).
activity monitors
description,
1-19
state transition flowchart (figure),
1-20
auto low-speed logic,
1-40
battery-management logic,
1-32
–
1-34
AC Input Status (ACIN) pin,
1-34
Battery Level 1 (BL1) pin,
1-32
Battery Level 2 (BL2) pin,
1-32
–
1-33
Battery Level 3 (BL3) pin,
1-33
Battery Level 4 (BL4) pin,
1-33
–
1-34
functionality of BL4-BL1 (table),
1-32
clock-switching logic,
1-16
–
1-18
clock startup and shutdown logic,
1-16
logic flowchart (figure),
1-18
CPU/memory clock switching,
1-16
data-path disabling logic,
1-41
DMA clock stop,
1-41
external-device control interface,
1-14
–
1-15
Latched Power pin,
1-15