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| 型號(hào)： | 20665 |
| 英文描述： | ?lanSC310 Programmer＇s Reference Manual |
| 中文描述： | ？lanSC310程序員參考手冊(cè) |
| 文件頁(yè)數(shù)： | 49/186頁(yè) |
| 文件大小： | 918K |
| 代理商： | 20665 |
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1-38
Power Management
1.9.4
Suspend Pseudocode
1. The PMU Status 1 register at Index A2h is written in order to clear the PMU SMI
request to the CPU.
2. Platform-dependent code prepares the system for the suspend operation.
3. The bit location in the SMM RAM state-save area that contains the value of bit 12 of
DR7 (the processor’s state) must be cleared. This handles an élanSC310 microcon-
troller CPU errata where bit 12 of DR7 is automatically set prior to the SMM state
save. If this bit is not cleared in the SMM state-save area prior to the CPU executing a
RES3 instruction, the erroneous bit is reloaded into DR7 and the trace opcode (F1h) is
redefined as a softSMI. The next trace instruction causes a soft SMI to occur.
4. The NMI/SMI Control register at Index A5h is read to determine if any additional SMI
events have occurred while processing the suspend SMI. These additional events
should also be processed or they will be lost.
5. The NMI/SMI Control register is written, which causes the PMU to exit Temporary-On
mode on the next refresh and transition from Sleep to Suspend mode. At the same
time, the ability of the next rising edge on the SUS/RES input to generate a wake-up
into High-Speed PLL mode is converted to immediate instead of buffered.
6. At this point, the SMI handler polls bit 4 of the AT-Compatible B port (61h), looking for
at least one refresh. Each time the bit toggles, a refresh has occurred. This must be
done to ensure that the PMU transition into Suspend mode occurs before any more of
the suspend SMI handler is executed. The CPU clock thus stops before the RES3
instruction is executed. This is done to prevent control from being returned to the appli-
cation that was interrupted by the SMI. This should be avoided because the system
has been prepared for Suspend mode. Peripheral devices may have been turned off,
which causes errors if accessed in this state.
The CPU clock is now stopped and the system is suspended. From this point on, an edge
on the SUS/RES pin is considered a resume input. Note that although RES3 has not
been executed by the CPU (thus ending the suspended SMI), all remaining suspend-SMI
code after this is processed as the result of a resume input. The effect is that the last few
instructions of the suspend handler (everything before RES3) are really the first few
instructions of the resume code. This is not to say that the resume SMI entry point is any-
where in the suspend SMI handler. The remainder of the handler execution follows:
7. A resume input is detected. This transitions the PMU into High-Speed PLL mode and
causes it to assert an SMI request to the CPU. Note that the SMI request is not seen
by the CPU at this point because RES3 has not been generated for the suspend SMI.
8. The CPU RES3 instruction is executed to signal the end of the SMI routine. This
allows the CPU to detect pending SMIs asserted by the PMU. As a result of the pend-
ing SMI request, an SMI is generated immediately, and the SMI routine is entered to
process the resume.
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相關(guān)代理商/技術(shù)參數(shù) |
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| 20-665000-00 | 功能描述:IC 與器件插座 SOWIC TO SOIC ADAPT 20 PINS RoHS:否 制造商:Molex 產(chǎn)品:LGA Sockets 節(jié)距:1.02 mm 排數(shù): 位置/觸點(diǎn)數(shù)量:2011 觸點(diǎn)電鍍:Gold 安裝風(fēng)格:SMD/SMT 端接類型:Solder 插座/封裝類型:LGA 2011 工作溫度范圍:- 40 C to + 100 C |
| 20-665000-00-P | 制造商:ARIES 制造商全稱:Aries Electronics, Inc. 功能描述:SOWI-to-SOIC Adapter |
| 206650-1 | 制造商:TE Connectivity 功能描述:206650-1 |
| 2066531 | 制造商: 功能描述: 制造商:TE Connectivity 功能描述: 制造商:undefined 功能描述: |
| 206653-1 | 制造商: 功能描述: 制造商:undefined 功能描述: |
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