
4-60
Configuration Registers
4.3.85
PMU Control 3 Register (Index ADh)
This register controls several PMU functions. When switching the low-speed frequency,
the low-speed PLL is divided. This divided frequency is selected for use when the PMU is
not in the Low-Speed PLL mode. The Low-Speed Clock Select bits (bits 1 and 0 of the
PMU Control 3 register) should be modified only when the PMU is not in Low-Speed PLL
mode.
Bit 4
Index 75h. If bit 4 of the PMU Control 3 register is 0, bit 6 of the Activity Mask 1 register
has no function.
This bit is used in conjunction with bit 6 of the Activity Mask 1 register at
Bits 1–0
These bits only have an effect in Low-Speed PLL mode.
4.3.86
Reserved Register (Index AEh)
This register is reserved.
7
0
Field
Bit
Default
Clock Select
ONCLK1
0
(Reserved)
0
IRQ0SMIEN
0
(Reserved)
0
ENACIN
0
XTKBDEN
0
MAINOFF
0
ONCLK0
0
Bit
Name
R/W
Function
7
6
R/W
R/W
(Reserved)
1 = 8254 channel 0 generates an SMI instead of the normal IRQ0. Note that
the IRQ0 in the PIC must be enabled to allow this condition.
(Reserved)
1 = ACIN is treated as activity
1 = Allows the 8042CS and SYSCLK pins to become three-stated so they
may be used as inputs, all other requirements being met. It also qualifies an
internal decode so that port 60h is read as an internal port. It further switches
a multiplexer to vector IRQ1 from the external pin to the output of this
circuitry.
1 = élanSC310 microcontroller turns off the high-speed PLL in Low-Speed
PLL mode; otherwise, the high-speed PLL is turned off in Doze mode.
Low-Speed PLL mode CPU clock bit 1
Low-Speed PLL mode CPU clock bit 0
IRQ0SMIEN
5
4
3
R/W
R/W
R/W
ENACIN
XTKBDEN
2
MAINOFF
R/W
1
0
ONCLK1
ONCLK0
R/W
R/W
Table 4-35
Low-Speed PLL Mode CPU Clock Speed Select
ONCLK1
ONCLK0
Clock Frequency to CPU
Internal CPU Operation Speed
0
0
9.216 MHz
4.608 MHz
0
1
4.608 MHz
2.304 MHz
1
0
2.304 MHz
1.152 MHz
1
1
1.152 MHz
0.576 MHz