
4-12
Configuration Registers
4.3.3
Resume Status Register (Index 09h)
A 1 in any bit in this register indicates that the corresponding function caused the system
to wake up. 00h must be written to this register to clear it.
4.3.4
Reserved Registers (Indexes 0A-0Eh)
These index locations are reserved.
4.3.5
Reserved Register (Index 0Fh)
This index location is reserved and must be initialized to FFh at boot time.
4.3.6
Reserved Registers (Indexes 10–39h)
These index locations are reserved.
4.3.7
I/O Timeout Register (Index 40h)
This register may be used with the SMI Enable register at Index 41h to determine if an
I/O-device access generates an SMI. If a bit in this register is 0 and the corresponding bit
in the SMI Enable register is 1, the next I/O access to that device causes an SMI.
In addition, writing a 0 to a bit enables an SMI to occur on the next I/O access to that
device. Writing a 1 has no effect. For more information, see “Accesses to Powered-Down
Device SMI” on page 1-29.
7
0
Bit
Default
(Reserved)
PRIM_RI
0
IRQ8
0
IRQ4
0
IRQ3
0
(Reserved)
0
0
0
0
Bit
Name
R/W
Function
7–6
5
4
3
2
1-0
R/W
R/W
R/W
R/W
R/W
R/W
(Reserved)
System was awakened by a Ring-In from the internal UART
System was awakened by IRQ8
System was awakened by IRQ4
System was awakened by IRQ3
(Reserved)
PRIM_RI
IRQ8
IRQ4
IRQ3
7
0
Bit
Default
(Reserved)
0
PIOTOLTCH FDTOLTCH
0
HDTOLTCH
0
0
0
0
0
0
Bit
Name
R/W
Function
7–3
2
1
R/W
R/W
R/W
(Reserved)
1 = PIO access caused the SMI; PIO SMIs are masked until this bit is 0
1 = Floppy disk drive access caused the SMI; floppy-disk-drive SMIs are
masked until this bit is 0
1 = Hard disk drive access caused the SMI; hard-disk-drive SMIs are
masked until this bit is 0
PIOTOLTCH
FDTOLTCH
0
HDTOLTCH
R/W