
1-2
Power Management
1.1
POWER MANAGEMENT UNIT
The primary design goal of the Power Management Unit (PMU) is to control the power of
the entire system so as to eliminate or minimize the excess use of current, particularly
when it is not needed at a specific time. The PMU uses the following techniques to con-
serve power:
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Slows down clocks when the system is not in active use
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Shuts off clocks to parts of the system that are idle
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Shuts off power to parts of the system that are idle
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Reduces power use when batteries are low
An additional goal of a good PMU design is to make these functions as transparent to the
user as possible and to avoid any possibility of disastrous side effects, such as accidental
loss of data. The élanSC310 microcontroller’s PMU includes the following principal
components:
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PMU State Machine
transitions. Depending on the current level of activity registered by the PMU state, the
system may, for example, run clocks at a high speed, a low speed, or turn them off.
The current and previous PMU states may be read; in addition, the PMU may be
forced into a specific state by a software command.
Defines certain levels of system activity and the allowable state
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External Device-Control Interface
switches to different devices. The on or off status of most of these devices may be
specifically programmed for each of the available power-management states. In addi-
tion, dedicated logic enables the power to three specific devices to be automatically
turned off after a specified time-out period during which no activity has occurred. If one
of these devices is accessed after power has been turned off, an SMI is automatically
generated so that the I/O instruction can be retried after powering up the device.
Allows the PMU to control external power
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Clock-Switching Logic
clock, or switches off the CPU clock and phase-locked loops (PLLs).
Synchronously switches different clock sources to the CPU
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Activity Monitors
activity. On receipt of an event, this logic causes the PMU state machine to switch to
High-Speed PLL mode. By definition, activities function only while the CPUCLK signal
is running.
Check for certain external or CPU events that indicate system
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State-Transition Timer
changes occur.
Defines the allowable periods of inactivity before PMU state
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Wake-Up Logic
PLLs. Wake-ups are independent of whether the CPUCLK signal is on or off. Wake-
ups force the PMU into High-Speed PLL mode.
Allows certain events to start the clocks and restart the on-board
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NMI and SMI Control
to generate a nonmaskable interrupt (NMI) or SMI to the CPU. If the CPU clock is not
running when a triggering event occurs, this logic can cause the PMU to start the CPU
clock to process the interrupt.
Allows certain external, internally generated, or CPU events
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Battery-Management Logic
levels can be programmed to generate SMIs or NMIs, slow the CPU clock, or force the
system into Sleep or Suspend mode.
Includes four levels of battery-power handling. Certain
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Suspend and Resume Pin Logic
PMU to enter Sleep mode or to wake up from Sleep, Suspend, or Off mode.
Provides a user-operable method of forcing the