
INDEX
I-19
external SMI
with multiple devices,
1-31
with single device,
1-31
external SMI pin,
1-31
processing NMI or SMI source,
1-28
SMI processing flowchart (figure),
1-26
sources for generating SMIs,
1-28
Temporary-On mode,
1-26
–
1-27
treatment of pending SMIs,
1-31
SMI Enable Register (Index 41h)
bit descriptions,
4-13
powered-down device SMIs,
1-30
–
1-31
using with I/O Timeout Register (Index 40h),
4-12
SMI I/O Status Register (Index 42h)
bit descriptions,
4-14
powered-down device SMIs,
1-30
SMI MMS Page Register (Index AAh)
bit descriptions,
4-57
enabling SMIs,
1-27
SMI MMS Upper Page Register (Index A9h)
enabling SMIs,
1-27
selecting SMI or NMI,
4-43
SMI Status Register (Index 43h)
bit descriptions,
4-14
determining source of SMIs,
1-28
SMIA14 bit,
4-57
SMIA15 bit,
4-57
SMIA16 bit,
4-57
SMIA17 bit,
4-57
SMIA18 bit,
4-57
SMIA19 bit,
4-57
SMIA20 bit,
4-57
SMIA21 bit,
4-57
SMIA22 bit,
4-57
SMIA23 bit,
4-57
SMIs
generation by BL2 and BL3,
1-33
overview,
1-1
,
1-2
registers for controlling and determining status (ta-
ble),
4-10
resume input causing SMI,
1-39
SMI-generation settings for PIO access example (ta-
ble),
1-13
suspend input causing SMI,
1-37
suspend/resume operation,
1-35
start of SMI handler,
1-37
timer-controlled shutdown using SMI interface,
1-14
–
1-15
SMM RAM state-save area
resume pseudocode,
1-39
suspend pseudocode,
1-38
Software Mode Control Register (Index 88h)
avoiding incoherency in SMI or NMI state-transitions,
1-29
bit descriptions,
4-45
PMU mode select logic (table),
4-45
SOUTL bit,
4-28
SP bit
Line Control Register (Ports 2FBh & 3FBh),
3-13
NMI/SMI Control Register (Index A5h),
4-56
SP0 bit,
4-59
SP1 bit,
4-59
SP2 bit,
4-43
SP3 bit,
4-58
SP4 bit,
4-58
SPC0 bit,
4-45
SPC1 bit,
4-45
SPC2 bit,
4-45
SPEED bit,
4-22
SPKD bit,
3-20
SQWE bit,
3-19
state machine. SeePMU state machine.
State-Transition Timer,
1-22
–
1-23
definition,
1-2
events causing reset,
1-23
programming with Mode Timer registers,
1-22
registers for controlling (table),
4-10
state-transitions
avoiding incoherency in SMI or NMI state-transitions,
1-28
–
1-29
flowchart (figure),
1-20
stepping level, determining. SeeVersion Register (In-
dex 64h).
STP bit,
3-13