
Configuration Registers
4-51
4.3.69
General-Purpose I/O 1 Register (Index 9Ch)
This is a write-only register. It is used to control the PGP1 pin in either direct-control
mode or address-decode mode when PGP1 is configured as an output. In direct-control
mode, the state of PGP1 is controlled by bit 7. When bit 7 is 1, PGP1 is Low. When bit 7 is
0, PGP1 is High. In address-decode mode, PGP1 functions as a simple address decode.
PGP1 is High until the SA9–SA3 signals match bits 6–0 of this register, at which time
PGP1 goes Low for as long as the signals match. PGP1 can also be gated internally with
the I/O Read command signal. The General-Purpose I/O Control register at Index 91h is
used to select how PGP1 operates as an output. Bit 2 of the MMSB Control register at
Index 74h is used for PGP1 direction control.
4.3.70
Reserved Register (Index 9Dh)
This index location is reserved and must be set to 40h.
4.3.71
Auto Low-Speed Control Register (Index 9Fh)
This register controls the auto low-speed trigger and duration period. Bit 3 of the
Control B register at Index 77h disables or enables the trigger; bit 6 of the I/O Wait State
register at Index 61h enables the high-speed CPU clock.
Table 4-30
Hit-Count Limit Bit Logic
Bit
1
2
0
Hit-Count Limit
0
0
0
1
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
128
Notes:
The hit count is cleared when a PMU state-transition counter expires or any other activity occurs. Thus, all
memory writes must occur in the same PMU state, without other activity, before they count as activity.
If the hit-count limit is 2 and two or more memory write cycles fall into the range specified by the address
range, it counts as activity. If bit 0 of the Memory Write Activity Lower Boundary register at Index 9Ah is not
set, then this function is disabled.
7
0
Field
Bit
Default
Address Bits 9–3
A6
0
DX
0
A9
0
A8
0
A7
0
A5
0
A4
0
A3
0