
4-46
Configuration Registers
4.3.54
General-Purpose I/O 0 Register (Index 89h)
This is a write-only register. This register is used to control the PGP0 pin in either direct-
control mode or address-decode mode when PGP0 is configured as an output. In direct-
control mode, the state of PGP0 is controlled by bit 7. When bit 7 is 1, the PGP0 output is
Low. When bit 7 is 0, PGP0 is High. In address-decode mode, PGP0 functions as a sim-
ple address decode. PGP0 is High until the SA9–SA3 signals match bits 6–0 of this regis-
ter, at which time PGP0 goes Low for as long as the signals match. PGP0 can also be
gated internally with the I/O Write command signal. The General-Purpose I/O Control
register at Index 91h is used to select how PGP0 operates as an output. Bit 6 of the
Miscellaneous 6 register at Index 70h is used for PGP0 direction control.
4.3.55
Reserved Registers (Indexes 8A-8Bh)
These index locations are reserved.
4.3.56
I/O Activity Address 0 Register (Index 8Ch)
This register is used by the PMU software to program the I/O address that the activity
monitor checks (bit 4 of the Activity Mask 2 register at Index 76h is the mask). This is a
write-only register. Status is read from bit 4 of the Activity Status 2 register at Index A1h.
4.3.57
I/O Activity Address 1 Register (Index 8Dh)
This register is used by the PMU software to program the I/O address that the activity
monitor checks (bit 5 of the Activity Mask 2 register at Index 76h is the mask). This is a
write-only register. Status is read from bit 5 of the Activity Status 2 register at Index A1h.
4.3.58
Reserved Register (Index 8Eh)
This index location is reserved.
7
0
Field
Bit
Default
Address Bits 9–3
A7
0
DX
0
A9
0
A8
0
A6
0
A5
0
A4
0
A3
0
7
0
Field
Bit
Default
I/O Address, Bits 9–3
A7
0
(Reserved)
0
A9
0
A8
0
A6
0
A5
0
A4
0
A3
0
7
0
Field
Bit
Default
I/O Address, Bits 9–3
A6
0
(Reserved)
0
A9
0
A8
0
A7
0
A5
0
A4
0
A3
0