
INDEX
I-5
floppy disk drive wait states (table),
4-22
hard drive wait states,
4-23
SMI Enable Register (Index 41h),
4-13
SMI Status Register (Index 43h),
4-14
disk drives, powered-down,
1-29
–
1-31
DISREFOFF bit,
4-69
DISW bit,
4-27
divider-chain bits, time-base (table),
3-18
Divisor Latch Lower Byte (Ports 2F8h & 3F8h),
3-12
Divisor Latch Upper Byte (Ports 2F8h & 3F9h),
3-12
DLAB bit,
3-13
DM bit,
3-19
DMA access, controlling (table),
4-6
DMA clock
clock stop feature,
1-41
PMU clock speeds (table),
1-6
DMA Controller Registers
DMA Controller 1 addresses (table),
3-5
DMA Controller 2 addresses (table),
3-7
DMA Page Registers,
3-7
–
3-8
DMAMMS bit,
4-22
DMASTCLK bit,
4-61
DMWS bit,
4-34
Documentation
Contents of Manual,
xii
Literature Fulfillment Service,
xii
Purpose of this Manual,
xi
Related AMD Publications,
xii
DOS chip-select signal
DOSCS wait-state control-bit logic (table),
2-16
high-speed clock ROM cycles,
2-15
purpose and use,
2-16
DOSCS signal
accessing ROM DOS memory,
2-8
address decode (table),
4-68
controlling with ROM Configuration 3 Register (Index
B8h),
4-67
DOS chip-select signal,
2-8
high-speed clock ROM cycles,
2-15
number of wait states of DOSCS cycle (table),
4-67
ROM chip-select command gating,
2-14
ROM chip-select signal,
2-15
wait-state control-bit logic (table),
2-16
Doze mode. See alsoLow-Speed to Doze Timer Regis-
ter (Index 84h).
1-5
–
1-6
Doze to Sleep Timer Register (Index 85h)
description,
4-44
state-transition timing,
1-22
DR bit,
3-14
DRAM
80-ns DRAM support,
2-17
8254-based DRAM refresh,
2-3
configurations,
2-2
DRAM bank miss wait state select logic (table),
4-25
DRAM first cycle wait state select logic (table),
4-25
Enhanced Page mode,
2-4
memory configuration (DRAM (table),
4-28
memory initialization example (table),
2-3
Page-mode DRAMs,
2-4
registers for setting up (table),
4-7
self-refresh DRAMs,
2-17
slow refresh,
2-3
Drive Timer Register (Index 47h)
bit descriptions,
4-17
hard drive and floppy disk drive timer setting bit logic
(table),
4-18
DRLSD bit,
3-15
DRQ pins as wake-up signals,
1-24
DRQ0 bit,
4-53
DRQ1 bit
Activity Mask 1 Register (Index 75h),
4-40
Activity Status 1 Register (Index A0h),
4-53
DRQ1 signal (table),
1-23
DRQ2 bit
Activity Mask 1 Register (Index 75h),
4-40
Activity Status 1 Register (Index A0h),
4-53
DRQ2 signal (table),
1-23
DRQ3 bit
Activity Mask 1 Register (Index 75h),
4-40
Activity Status 1 Register (Index A0h),
4-53
DRQ3 signal (table),
1-23
DRQ5 signal (table),
1-23
DRQ6 signal (table),
1-23
DRQ7 signal (table),
1-23