
Power Management
1-27
normal operation for the mode it was previously in, except that for a mode-change SMI,
the PMU will advance to the next PMU mode after leaving Temporary-On mode. Note that
if the PMU was in High-Speed PLL mode when receiving a battery-level-change SMI or
NMI, it does not slow down the clock, but continues running at High-Speed PLL mode
clock rates. While the PMU is in Temporary-On mode, all activities, wake-up events, and
PMU mode transition timers are disabled. However, activities and wake-up events are
internally latched and cause the appropriate action to be taken when exiting Temporary-
On mode.
When the system SMI handler determines that an SMI has been generated from the first
three sources, the write to the NMI/SMI Control register at Index A5h should always be
performed at the end of the SMI handler. The NMI/SMI Control register should be read
just prior to writing to it. If any additional SMI flags are set, they should be processed prior
to writing the NMI/SMI Control register.
In some cases, it may be important to ensure that the CPU clocks are stopped prior to
exiting the SMI/NMI routine. This prevents the main code from accessing a device that
was just powered down in the routine. This can be accomplished by polling the Port B
register for a refresh after the write to the NMI/SMI Control register. The clocks are
stopped when the refresh occurs. When the clocks start again, the SMI/NMI routine fin-
ishes executing.
1.7.2
Enabling SMIs
To enable SMI generation, bit 7 of the MMSB Socket register at Index A9h must be 1. If
bit 7 is 0, the first three SMI and NMI sources generate NMIs instead of SMIs. When
enabling SMIs, the SMI MMS Page register at Index AAh and bits 4 and 5 of the MMSB
Socket register must be programmed to set the MMS page where SMI CPU core data will
be preserved. Bit 0 of the Miscellaneous 2 register at Index 6Bh gives the programmer
the option of forcing address bit 20 Low during SMI routines.
Table 1-9 on page 1-27 shows the registers that enable the various SMI sources.
Table 1-9
Registers that Enable SMI Sources
Register Name
Index
SMI Enable
41h
NMI/SMI Control
A5h
Function Enable 1
B0h
PMU Control 3
ADh
NMI/SMI Enable
82h