
vi
Table of Contents
4.3.62
4.3.63
4.3.64
4.3.65
4.3.66
4.3.67
4.3.68
4.3.69
4.3.70
4.3.71
4.3.72
4.3.73
4.3.74
4.3.75
4.3.76
4.3.77
4.3.78
4.3.79
4.3.80
4.3.81
4.3.82
4.3.83
4.3.84
4.3.85
4.3.86
4.3.87
4.3.88
4.3.89
4.3.90
4.3.91
4.3.92
4.3.93
4.3.94
4.3.95
4.3.96
UART Clock Enable Register (Index 92h). . . . . . . . . . . . . . . . .4-49
Reserved Register (Index 93h). . . . . . . . . . . . . . . . . . . . . . . . .4-49
General-Purpose I/O 2 Register (Index 94h) . . . . . . . . . . . . . .4-49
General-Purpose I/O 3 Register (Index 95h) . . . . . . . . . . . . . .4-49
Reserved Registers (Indexes 96–99h) . . . . . . . . . . . . . . . . . . .4-49
Memory Write Activity Lower Boundary Register (Index 9Ah) .4-50
Memory Write Activity Upper Boundary Register (Index 9Bh) .4-50
General-Purpose I/O 1 Register (Index 9Ch) . . . . . . . . . . . . . .4-51
Reserved Register (Index 9Dh) . . . . . . . . . . . . . . . . . . . . . . . .4-51
Auto Low-Speed Control Register (Index 9Fh) . . . . . . . . . . . . .4-51
Activity Status 1 Register (Index A0h) . . . . . . . . . . . . . . . . . . .4-53
Activity Status 2 Register (Index A1h) . . . . . . . . . . . . . . . . . . .4-53
PMU Status 1 Register (Index A2h) . . . . . . . . . . . . . . . . . . . . .4-54
CPU Status 0 Register (Index A3h) . . . . . . . . . . . . . . . . . . . . .4-54
CPU Status 1 Register (Index A4h) . . . . . . . . . . . . . . . . . . . . .4-55
NMI/SMI Control Register (Index A5h) . . . . . . . . . . . . . . . . . . .4-56
Reserved Register (Index A6h). . . . . . . . . . . . . . . . . . . . . . . . .4-56
PMU Control 1 Register (Index A7h). . . . . . . . . . . . . . . . . . . . .4-56
Reserved Register (Index A8h). . . . . . . . . . . . . . . . . . . . . . . . .4-57
SMI MMS Upper Page Register (Index A9h) . . . . . . . . . . . . . .4-57
SMI MMS Page Register (Index AAh). . . . . . . . . . . . . . . . . . . .4-57
Power Control 3 Register (Index ABh) . . . . . . . . . . . . . . . . . . .4-58
Power Control 4 Register (Index ACh) . . . . . . . . . . . . . . . . . . .4-59
PMU Control 3 Register (Index ADh) . . . . . . . . . . . . . . . . . . . .4-60
Reserved Register (Index AEh) . . . . . . . . . . . . . . . . . . . . . . . .4-60
PMU Control 2 Register (Index AFh) . . . . . . . . . . . . . . . . . . . .4-61
Function Enable 1 Register (Index B0h). . . . . . . . . . . . . . . . . .4-61
Function Enable 2 Register (Index B1h). . . . . . . . . . . . . . . . . .4-62
PIRQ Configuration Register (Index B2h). . . . . . . . . . . . . . . . .4-64
Miscellaneous 5 Register (Index B3h) . . . . . . . . . . . . . . . . . . .4-65
Function Enable 3 Register (Index B4h). . . . . . . . . . . . . . . . . .4-66
Reserved Registers (Indexes B5h-B7h) . . . . . . . . . . . . . . . . . .4-66
ROM Configuration 3 Register (Index B8h) . . . . . . . . . . . . . . .4-67
Memory Configuration 2 Register (Index B9h) . . . . . . . . . . . . .4-69
Miscellaneous 3 Register (Index BAh) . . . . . . . . . . . . . . . . . . .4-70
Appendix A
CONFIGURATION INDEX
REGISTER REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-1
Appendix B
XT-KEYBOARD INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .B-1
INDEX