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| 型號(hào)： | 20665 |
| 英文描述： | ?lanSC310 Programmer＇s Reference Manual |
| 中文描述： | ？lanSC310程序員參考手冊(cè) |
| 文件頁(yè)數(shù)： | 18/186頁(yè) |
| 文件大?。?/td> | 918K |
| 代理商： | 20665 |
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Power Management
1-7
1.1.1.4
Sleep Mode
Sleep mode is the third level of power conservation. In addition to the clocks disabled in
Doze mode, the keyboard clock (external SYSCLK signal) is disabled, regardless of
whether the low-speed PLL is enabled. Sleep mode is entered after a programmable time
without activity has elapsed. For details, see “Doze to Sleep Timer Register (Index 85h)”
on page 4-44.
In this mode, the CPU, system, and DMA clocks are stopped and cannot be restarted
unless one of the following events occurs:
I
An SMI or NMI on BL1 or BL3 (when enabled)
I
An SMI or NMI generated on a change to Suspend mode
I
A wake-up event causes an exit from Sleep mode to High-Speed PLL mode
In the first two cases, the clock runs only during the SMI or NMI routine and then stops
again. The keyboard clock is also shut down and can only be restarted by waking up to
High-Speed PLL mode. The high-speed PLL is always shut down in Sleep mode.
By setting bit 3 of the Power Control 2 register at Index 81h, the low-speed PLL and video
PLL also may be shut down in this mode. In this case, the low-speed and video PLL is
restarted before responding to an SMI or NMI or changing to High-Speed PLL mode.
When changing to High-Speed PLL mode, the high-speed PLL is also restarted. Note
that the low-speed PLL is divided to generate the 8254 timer clock.
The PMC pins may be programmed to a specific state for Sleep mode. An NMI or SMI
may be generated upon entering Sleep mode, in which case the handler runs at 9.2 MHz.
1.1.1.5
Suspend Mode
With regard to the clocks and PLLs, Suspend mode has the same functionality as Sleep
mode. But bit 7 of the Power Control 2 register at Index 81h enables shutdown of the
video and low-speed PLLs in Suspend mode. The distinction between Suspend and
Sleep mode is in the way the external Power-Management Control (PMC) pins behave
and may be programmed to behave. The PMC pins may be programmed to a specific
state for this mode. An NMI or SMI may be generated upon entering Suspend mode, in
which case the handler runs at 9.2 MHz.
1.1.1.6
Off Mode
Off is a powered-down mode in which the Programmable General-Purpose 2 and 3
(PGP2 and PGP3) pins are set to a predefined state, and memory refresh may be dis-
abled. The state of the PGP pins is determined by the General-Purpose I/O 2 and 3 regis-
ters at Indexes 94h and 95h, and the General-Purpose I/O Control register at Index 91h.
The system cannot be programmed to enter Off mode directly. The only method of Off
mode entry is by expiration of the Suspend to Off Mode Timer register at Index 87h.
When this happens, the PMU state machine is left in Suspend mode, and an internal,
nonreadable flip-flop is set, indicating Off mode. An NMI or SMI may be generated upon
entering Off mode.
Refresh may be programmed to be disabled when the PMU is in Off mode. Setting bit 7 of
the Memory Configuration 2 register at Index B9h causes the RAS and CAS outputs to
be driven Low when the PMU is in Off mode. The system logic should power off the
DRAM in this mode, or the Low RAS and CAS outputs may keep the row buffers enabled,
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