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| 型號(hào)： | 20665 |
| 英文描述： | ?lanSC310 Programmer＇s Reference Manual |
| 中文描述： | ？lanSC310程序員參考手冊(cè) |
| 文件頁數(shù)： | 20/186頁 |
| 文件大?。?/td> | 918K |
| 代理商： | 20665 |
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Power Management
1-9
1.1.3
PMU Clock Sources
The élanSC310 microcontroller’s PMU uses the 32-kHz clock to derive its internal timing.
This clock runs off the élanSC310 microcontroller’s internal oscillator, which cannot be
disabled. Many events are synchronized with the internal refresh signal, which by default
is derived from the 32-kHz clock. If the élanSC310 microcontroller’s PMU is being used in
a system design, the refresh clock must not be set to Timer Channel 1 because the timer
is disabled in some PMU modes.
The remainder of this section describes the functionality of the system during each of the
PMU states. Later sections discuss the different ways the PMU can be caused to enter
these states.
1.1.4
Reading the PMU Mode
The current PMU mode can be read from the CPU Status 1 register at Index A4h. If the
PMU is in the Off mode, this register indicates Suspend mode. PMU mode changes
always take effect on the next refresh after the mode change was registered. The mode
that is read from the CPU Status 1 register at Index A4h is one refresh delay in advance
of the internal signals that actually execute the functions of the PMU mode. Therefore, if it
is necessary to know the exact mode of the PMU at a specific time (e.g., for the purpose
of determining the state of the PMC signals), the software must read the CPU Status 1
register on two successive refreshes and verify that the mode has not changed.
1.1.5
Merging of PMU Modes
Although six PMU modes are defined, the system designer may reduce the effective
number of PMU modes by defining identical functions for some of the modes. For exam-
ple, assuming that Full-ISA or Local-Bus modes are being used, a three-mode system
that effectively merges the Doze, Sleep, Suspend, and Off modes can be achieved. To
merge the Doze, Sleep, Suspend, and Off modes, use the following procedure:
1. Set bit 7 of the Power Control 1 register at Index 80h and bits 3 and 7 of the Power
Control 2 register at Index 81h to disable the low-speed and video PLLs in Doze,
Sleep, and Suspend modes.
2. Set all the PMC bits to the same value for Doze, Sleep, and Suspend modes.
3. Do not enable the PGP2 and PGP3 pins to change in Off mode.
The net effect of this procedure is to create a three-mode system, effectively consisting of
High-Speed PLL, Low-Speed PLL, and Suspend modes, where Doze, Sleep, Suspend,
and Off modes have been merged into a single new
pseudo-Suspend
mode.
1.1.6
Programming Example: Power-Management Setup
Neglecting peripheral control for the moment, the first step in setting up power-manage-
ment for a system is to define what constitutes
activity:
activity
. The following events constitute
I
DMA requests and interrupt requests (DRQ, IRQ)
I
Keyboard, LPT, COM, and programmable I/O port accesses
I
MMS, video memory, and programmable memory range accesses
I
Hard disk drive and floppy disk drive accesses
I
AC adapter active (rising edge of ACIN)
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參數(shù)描述 |
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| 20-665000-00-P | 制造商:ARIES 制造商全稱:Aries Electronics, Inc. 功能描述:SOWI-to-SOIC Adapter |
| 206650-1 | 制造商:TE Connectivity 功能描述:206650-1 |
| 2066531 | 制造商: 功能描述: 制造商:TE Connectivity 功能描述: 制造商:undefined 功能描述: |
| 206653-1 | 制造商: 功能描述: 制造商:undefined 功能描述: |
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