
Power Management
1-33
The PMU may be programmed to automatically enter Sleep mode after a 0 is detected on
BL2 while ACIN is also at 0. This feature is enabled by clearing bit 6 of the MMSB Control
register at Index 74h, and is enabled by default. The PMU does not enter Sleep mode
instantaneously, but steps down a mode level on each refresh until Sleep mode is
reached. Once the PMU is in Sleep mode, the PMU state-transition timers control transi-
tions to Suspend and Off modes. Enabled wake-up/activity events will cause the PMU to
change to High-Speed PLL mode. However, the PMU will step down a mode level on
each refresh if the BL2 pin is Low. PMU state transition to Sleep mode can be temporarily
interrupted by enabling Low-to-Doze or Doze-to-Sleep mode-change NMI/SMI events in
the NMI/SMI Enable register at Index 82h.
SMIs may be generated by BL2. This feature is enabled by bit 6 of the NMI/SMI Enable
register. There are important differences between the SMI behavior of BL2 relative to BL1
and BL3. SMIs are generated only on falling edges of BL2. During the SMI handler, the
CPU must read the NMI/SMI Control register at Index A5h to reset the BL2 SMI genera-
tion logic. The SMI service routine must also write to the PMU Status 1 register at
Index A2h to clear the PMU SMI request.
SMIs from BL2 are masked in Sleep, Suspend, and Off modes and when pin BL4 is Low.
If an SMI from BL2 occurs in Doze mode and the CPU clock is stopped, the clock is
started to execute the SMI. The clock remains running until the next refresh cycle follow-
ing a write to the NMI/SMI Control register.
1.8.3
Battery Level 3
The Battery Level 3 (BL3) pin is intended to be used as a third-line warning, indicating
that battery power is low, but that enough power remains for limited use. The state of this
pin may be read directly at the CPU Status 0 register at Index A3h.
BL3 may also be programmed to generate SMIs. This feature is enabled by bit 7 of the
NMI/SMI Enable register at Index 82h. The functionality of this SMI is analogous to that of
the BL1 SMI.
An SMI generated by BL3 causes the CPU clock to be started, regardless of the PMU
mode (see “Temporary-On Mode” on page 1-26). The clock remains running until the next
refresh cycle following a write of 0 to the NMI/SMI Control register at Index A5h.
1.8.4
Battery Level 4
The Battery Level 4 (BL4) pin is intended to be used as an indication of the end of useful
battery life. It cannot be programmed to generate an SMI, and the state of BL4 cannot be
read.
The PMU may be programmed to automatically enter Suspend mode after a 0 is detected
on BL4 while ACIN is also 0. This feature is enabled by clearing bit 7 of the MMSB Con-
trol register at Index 74h and is enabled by default. The PMU does not enter Suspend
mode instantaneously, but steps down a mode level on each refresh until Suspend mode
is reached. Once the PMU is in Suspend mode, the PMU state-transition timers control
when (or if) there will be a transition to Off mode. After the PMU has been forced into this
condition, enabled wake-up/activity events will cause the PMU to transition to High-Speed
PLL mode. However, the PMU steps down a mode level on each refresh if the BL4 pin is
Low. PMU state transition to Suspend mode can be temporarily interrupted by enabling
Low-to-Doze, Doze-to-Sleep, or Sleep-to-Suspend mode-change NMI/SMI events in the
NMI/SMI Enable register at Index 82h.