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| 型號(hào)： | 20665 |
| 英文描述： | ?lanSC310 Programmer＇s Reference Manual |
| 中文描述： | ？lanSC310程序員參考手冊(cè) |
| 文件頁(yè)數(shù)： | 34/186頁(yè) |
| 文件大小： | 918K |
| 代理商： | 20665 |
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Power Management
1-23
The PMU timer is also reset by any of the following events:
I
An unmasked PMU activity event
I
A write to the Software Mode Control register at Index 88h
I
An SMI or NMI caused by the battery-level pins, a PMU mode change, or a SUS/RES
pin pulse (the timer is held in reset during one of the above SMIs until a write to the
NMI/SMI Control register at Index A5h occurs)
I
The high-speed or low-speed PLL is started (the timer is held in reset until startup is
completed)
WAKE-UP LOGIC
The élanSC310 microcontroller’s wake-up logic provides a mechanism for allowing cer-
tain external events to bring the PMU out of Sleep, Suspend, or Off mode into High-
Speed PLL mode. These events are defined in the Resume Mask register at Index 08h.
See Table 1-8 on page 1-23 for a list of the wake-up signals and associated trigger mech-
anisms. If the PMU is in Low-Speed PLL or Doze mode, these wake-up events function
as activities, returning the PMU to High-Speed PLL mode.
1.6
The events that may be allowed are Ring-Indicate signals from the internal UART, as well
as IRQ3 or IRQ4 (from the internal UART or an external pin, depending on the system
configuration) and IRQ8 (from the internal RTC only). In addition to the events defined in
the Resume Mask register, a rising edge on DRQ2 could be programmed as a wake-up
event through bit 2 of the Activity Mask 1 register at Index 75h. A rising edge on ACIN
may be enabled as a wake-up activity (bit 6 of the Activity Mask 1 register and bit 4 of the
PMU Control 3 register at Index ADh). And a rising edge on IRQ1 (AT keyboard interrupt)
could also be enabled as a wake-up activity (bit 4 of the Activity Mask 1 register). If the
Table 1-8
Wake-Up Signal Descriptions
Signal
Trigger
Description
DRQ1
Rising edge
Active until DRQ1 goes Low. Not maskable at the DMA controller.
DRQ2
Rising edge
Active until DRQ2 goes Low. Not maskable at the DMA controller.
DRQ3
Rising edge
Active until DRQ3 goes Low. Not maskable at the DMA controller.
DRQ5
Rising edge
Active until DRQ5 goes Low. Not maskable at the DMA controller.
DRQ6
Rising edge
Active until DRQ6 goes Low. Not maskable at the DMA controller.
DRQ7
Rising edge
Active until DRQ7 goes Low. Not maskable at the DMA controller.
IRQ1
Rising edge
Active until the keyboard controller deasserts IRQ1. Not maskable at the PIC.
IRQ3
Rising edge
Active until IRQ3 goes Low or channel 3 receives INT/ACK and EOI. Maskable
at the PIC.
IRQ4
Rising edge
Active until IRQ4 goes Low or channel 4 receives INT/ACK and EOI. Maskable
at the PIC.
IRQ8
Rising edge
Active until IRQ8 goes Low or channel 8 receives INT/ACK and EOI. Maskable
at the PIC.
RI
Falling edge
Active only until the next refresh. Clearing bit 5 of the Resume Status register
at Index 09h prior to the next refresh may not clear the RI activity status.
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| 20-665000-00 | 功能描述:IC 與器件插座 SOWIC TO SOIC ADAPT 20 PINS RoHS:否 制造商:Molex 產(chǎn)品:LGA Sockets 節(jié)距:1.02 mm 排數(shù): 位置/觸點(diǎn)數(shù)量:2011 觸點(diǎn)電鍍:Gold 安裝風(fēng)格:SMD/SMT 端接類(lèi)型:Solder 插座/封裝類(lèi)型:LGA 2011 工作溫度范圍:- 40 C to + 100 C |
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