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| 型號(hào)： | 20665 |
| 英文描述： | ?lanSC310 Programmer＇s Reference Manual |
| 中文描述： | ？lanSC310程序員參考手冊(cè) |
| 文件頁(yè)數(shù)： | 47/186頁(yè) |
| 文件大?。?/td> | 918K |
| 代理商： | 20665 |
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1-36
Power Management
Other issues that should be considered are as follows:
I
While processing a suspend input, an SMI occurs as a result of the Sleep-to-Suspend
transition (in this example). In order to process the SMI, the PMU enters Temporary-
On mode. Near the end of the SMI handler, a write of any value should be made to the
NMI/SMI Control register at Index A5h. This causes the PMU to transition into Sus-
pend mode on the refresh following the write to the NMI/SMI Control register.
I
When the PMU generates an SMI, a bit is set in the NMI/SMI Control register to indi-
cate to software which PMU event generated the SMI. Writing any value to the
NMI/SMI Control register clears this bit.
I
Prior to writing the NMI/SMI Control register, the register should be read again to
determine if any additional SMI events have occurred during the time it took to process
the previous event. If additional SMI events have occurred, they should also be pro-
cessed starting with a write to the PMU Status 1 register at Index A2h. Otherwise,
these events may be lost.
I
If in Temporary-On mode, activity on the SUS/RES pin is delayed until a write to the
NMI/SMI Control register occurs.
I
Temporary-On mode is not a PMU mode in the normal sense. Its state cannot be read
at the CPU Status 1 register at Index A4h like other PMU modes. It is really a special-
case state that turns on system clocks to allow the CPU to temporarily process instruc-
tions. This allows servicing an event that may occur while the PMU is in a clock-
stopped mode.
I
A suspend input causes further activity on the SUS/RES pin to be ignored until the
PMU has finished transitioning to Sleep mode.
I
The PMU can request that the processor perform an SMI. This request is in the form of
holding the CPU’s SMI signal active. The CPU ignores this request if it is already pro-
cessing an SMI, and it continues to do so until the SMI handler executes the RES3
instruction. The RES3 instruction signals the end of the SMI. If the PMU is asserting
an SMI request when RES3 is executed, another SMI signal is generated by the CPU.
Otherwise, control returns to the software that was initially interrupted by the SMI.
I
Once an SMI handler is entered, it must clear the PMU’s SMI request to the CPU. This
is done by writing any value to the PMU Status 1 register at Index A2h. The SMI CPU
input is level sensitive. As stated above, if a PMU SMI request is pending upon execu-
tion of RES3, another SMI is generated immediately by the CPU. This write to the
PMU Status 1 register should happen after the SMI Status register at Index 43h and
the NMI/SMI Control register at Index A5h are read to determine the cause of the SMI,
but before the SMI Status register and the NMI/SMI Control register are written in
order to clear their status.
I
When a resume input is serviced by the PMU, it places the PMU into Full-On mode
and then generates the resume SMI. In other words, the PMU is notin a Temporary-
On mode during this SMI. A suspend input at this point in the code will immediately
start transitioning the PMU towards Sleep mode.
I
The SMM memory area can be redirected through an MMS page at 060000h to point
to any location in system memory.
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