
I-12
INDEX
MISOUT bit
DRAM bank miss wait state select logic (table),
4-25
MMS Memory Wait State 1 Register (Index 62h),
4-23
MMS Address Extension 1 Register (Index 6Ch),
4-31
MMS Address Extension 2 Register (Index 6Eh),
4-33
MMS Address Register (Index 6Dh)
bit descriptions,
4-31
–
4-32
MMSA base addresses (table),
4-33
MMSA/B Page Register I/O Addresses (table),
4-32
page register contents description (table),
4-32
MMS bit,
4-53
MMS memory range select logic (table),
4-34
–
4-35
MMS Memory Wait State 1 Register (Index 62h)
16-bit ISA memory-cycle wait states (table),
4-24
8-bit ISA memory-cycle wait states (table),
4-24
bit descriptions,
4-23
setting up Page-mode DRAM accesses,
2-4
MMS Memory Wait State 2 Register (Index 50h)
bit descriptions,
4-19
ROM DOS command delay select logic (table),
4-19
ROM DOS wait state select logic (table),
4-19
MMS. SeeMemory Mapping System (MMS).
MMSA Address Extension 1 Register (Index 67h),
4-29
MMSA Device 1 Register (Index 71h)
bit descriptions,
4-36
page 0-3 device select (table),
4-36
MMSA Device 2 Register (Index 72h)
bit descriptions,
4-37
page 4-7 device select (table),
4-37
MMSABSEL bit,
4-39
MMSB Control Register (Index 74h)
bit descriptions,
4-39
enabling Sleep mode on Battery Level 2,
1-33
starting low-speed CPU clock,
1-6
MMSB Device Register (Index 73h)
bit descriptions,
4-38
page 0-3 device select (table),
4-38
MMSZ0 bit,
4-34
MMSZ1 bit,
4-34
MMSZ2 bit,
4-34
MMSZ3 bit,
4-34
MOD0 bit,
4-28
Modem Control Register (Ports 2FCh & 3FCh),
3-14
Modem Status Register (Ports 2FEh & 3FEh),
3-15
MRDLY bit,
4-34
MS0 bit
function,
4-28
memory configuration (DRAM) (table),
4-28
MS1 bit
function,
4-28
memory configuration (DRAM) (table),
4-28
MS2 bit
function,
4-28
memory configuration (DRAM) (table),
4-28
N
NENLB2 bit,
4-39
NENLB4 bit,
4-39
NFRDOSEN bit,
4-23
NFROMEN bit,
4-23
NMI/RTC Index Address Register (Port 070h),
3-21
NMI/SMI Control Register (Index A5h)
description,
4-56
enabling BL1 pin,
1-32
processing NMI or SMI source,
1-28
resume pseudocode,
1-39
SMI generation by BL2 pin,
1-33
suspend pseudocode,
1-38
suspend/resume operation,
1-36
Temporary-On-Mode,
1-26
–
1-27
NMI/SMI Enable Register (Index 82h)
bit descriptions,
4-43
enabling BL1 pin,
1-32
selecting NMI or SMI,
4-43
SMI generation by BL2 pin,
1-33
start of SMI handler,
1-37
NMIs. See alsoSMI and NMI control.
overview,
1-2
suspend/resume operation,
1-35
Nonmaskable Interrupt (NMI). See NMIs.
O
OE bit,
3-14
Off mode,
1-7
–
1-8