
I-10
INDEX
IRQ3 signal (table),
1-23
IRQ3MSK bit,
4-11
IRQ4 bit,
4-12
IRQ4 signal (table),
1-23
IRQ4MSK bit,
4-11
IRQ6 bit,
1-29
IRQ8 bit,
4-12
IRQ8 signal (table),
1-23
IRQ8MSK bit,
4-11
IRQEN bit
enabling hard-drive interrupt,
1-29
Miscellaneous 4 Register (Index 44h),
4-15
Parallel Control Port (Ports 27Ah & 37Ah),
3-10
Parallel Control Port (Ports 27Ah, 37Ah, & 37Eh),
3-9
IRQF bit,
3-19
ISA bus
configurations,
2-5
bus configuration (table),
2-5
élanSC310 microcontroller bus configurations (fig-
ure),
2-5
I/O access command delay, 8-bit (table),
4-20
memory access command delay, 8-bit (table),
4-21
memory-cycle wait states (table)
16-bit,
4-24
8-bit,
4-24
K
KB bit
Activity Mask 1 Register (Index 75h),
4-40
–
4-41
Activity Status 1 Register (Index A0h),
4-53
KBCLKEN bit,
3-20
KBSMIEN bit
SMI Enable Register (Index 41h),
4-13
SMI I/O Status Register (Index 42h),
4-14
keyboard clock, disabled in Sleep mode,
1-7
keyboard. SeeXT-keyboard interface.
L
latch and buffer logic (table),
4-62
Latched Power pin,
1-15
LIND0 bit,
4-54
LIND1 bit,
4-54
LIND2 bit,
4-54
Line Control Register (Ports 2FBh & 3FBh)
bit descriptions,
3-13
word length bit logic (table),
3-13
Line Status Register (Ports 2FDh & 3FDh),
3-14
LOOP bit,
3-14
LOW0 bit,
4-52
LOW1 bit,
4-52
low-speed CPU clock, controlling,
1-6
low-speed duration period select logic (table),
4-52
Low-Speed PLL mode
clock-switching logic,
1-16
logic flowchart (figure),
1-18
description,
1-5
low-speed PLL mode CPU clock speed select (table),
4-60
PMU operating-mode transitions,
1-8
Low-Speed to Doze Timer Register (Index 84h)
description,
4-44
state-transition timing,
1-22
LPH pin,
1-15
LPH1 bit,
4-54
LPT bit
Activity Mask 2 Register (Index 76h),
4-41
Activity Status 2 Register (Index A1h),
4-53
LSA14 bit,
4-50
LSA15 bit,
4-50
LSA16 bit,
4-50
LSA17 bit,
4-50
LSA18 bit,
4-50
LSA19 bit,
4-50
LSRWCNTL bit,
4-18
M
MAINOFF bit,
4-60
manual. Seedocumentation.
MCS16 signal,
4-66
,
4-67