
2-10
Memory Management
The MMS windows and their corresponding pages are set up by programming several
configuration registers in the élanSC310 microcontroller. In particular, control is exer-
cised through the following registers:
I
ROM Configuration 1 register at Index 65h
I
MMSA Address Extension 1 register at Index 67h
I
MMS Address Extension 1 and 2 registers at Indexes 6Ch and 6Eh
I
MMS Address register at Index 6Dh
I
MMSA Device 1 and 2 registers at Indexes 71h and 72h
I
MMSB Device register at Index 73h
I
MMSB Control register at Index 74h
All the index registers used in this section can be referenced in Appendix A, “Configura-
tion Index Register Reference,” as MMS registers except for the ROM Configuration 1
register. Bits 3–0 of the MMS Address register at Index 6Dh define the location in I/O
space of the eight MMSA and four MMSB page registers. Bit 1 of the MMSB Control reg-
ister at Index 74h determines whether the page-register I/O locations are accessing
MMSA page registers or MMSB page registers.
Each MMS window contains a global switch that enables or disables all the pages within
that window. Bit 5 of the ROM Configuration 1 register at Index 65h is the switch bit for
MMSA. Bit 0 of the MMSB Control register at Index 74h is the switch bit for MMSB.
As stated earlier, each MMS page is a fixed size of 16 Kbyte. Each page is mappable to
an equal-size page located on a 16-Kbyte boundary in one of the three address spaces:
ROM DOS, ROM BIOS, or on-board DRAM. Each individual page within an MMS window
can be enabled or disabled by setting or clearing a bit in its corresponding page register.
System RAM is not the default device that is accessed if an MMS window or a page of an
MMS window is disabled. This allows externally decoded, memory-mapped devices on
Figure 2-6
MMSA and MMSB
0F0000h
0E0000h
0D0000h
0C0000h
0B0000h
0A0000h
MMSA
High
Memory
MMSB