
I-16
INDEX
Power-Management Control (PMC4-PMC0) pins,
1-14
–
1-15
Programmable General-Purpose Pins 2 and 3,
1-15
Micro Power-Off mode,
1-40
overview,
1-1
quiet bus,
1-41
registers for managing (table),
controlling activities and events,
4-9
controlling power management state timers,
4-10
determining power management status,
4-9
resume pseudocode,
1-39
slow refresh,
1-41
SMI and NMI control,
1-25
–
1-31
accesses to powered-down device SMI,
1-29
–
1-31
device-powerdown flowchart (figure),
1-30
enabling SMIs,
1-27
external SMI
with multiple devices,
1-31
with single device,
1-31
external SMI pin,
1-31
processing flowchart (figure),
1-26
processing NMI or SMI source,
1-28
–
1-29
sources for generating SMIs,
1-25
state-transition timer,
1-22
–
1-23
suspend/resume pin logic,
1-34
–
1-39
avoiding problems,
1-39
capabilities required,
1-35
overview,
1-34
–
1-35
programming considerations,
1-36
required initialization,
1-37
resume input causing SMI,
1-39
resume inputs,
1-35
start of SMI handler,
1-37
suspend input causing SMI,
1-37
suspend inputs,
1-34
suspend pseudocode,
1-38
techniques,
1-1
temporary-on-mode,
1-26
–
1-27
treatment of pending SMIs,
1-31
wake-up logic,
1-23
–
1-24
powered-down device SMIs
description,
1-29
–
1-31
SMI device-powerdown flowchart (figure),
1-30
Power-Management Control (PMC4-PMC0) pins,
1-14
–
1-15
general-purpose control using PMU state machine,
1-14
PMC pin functionality (table),
1-14
purpose and use,
1-14
registers for setting up (table),
4-8
timer-controlled shutdown using SMI interface,
1-14
–
1-15
PPBIENB bit,
4-61
PPISBI bit,
4-61
PPOEN signal,
4-62
PRIM_RI bit,
4-12
Programmable General-Purpose Pins 2 and 3,
See alsoPGP pins, controlling.
1-15
Programmable Interval Timer Registers
description,
3-4
System Timer Registers (table),
3-5
pseudo-Suspend mode,
1-9
Q
quiet bus,
1-41
R
RA0 bit,
4-16
RA1 bit,
4-16
RAM mode decode logic (table),
4-63
RAS0 signal,
2-3
RAS1 signal,
2-3
RDOSCMDL bit
function,
4-19
ROM DOS command delay select logic (table),
4-19
RDOSSIZ3-RDOSSIZ0 bits
functions,
4-67
ROM DOS linear address decode size select logic
(table),
4-68
RDOSWS0 bit
function,
4-19
ROM DOS wait state select logic (table),
4-19
RDOSWS1 bit
function,
4-19
ROM DOS wait state select logic (table),
4-19
RDOSWSEN bit
function,
4-19
ROM DOS command delay select logic (table),
4-19
ROM DOS wait state select logic (table),
4-19
read only memory. See ROM BIOS memory.
reading PMU mode,
1-9
real-time clock
addressing,
3-16
overview,
3-16
Register A (RTC Index 0Ah)
bit descriptions,
3-17