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| 型號(hào)： | 20665 |
| 英文描述： | ?lanSC310 Programmer＇s Reference Manual |
| 中文描述： | ？lanSC310程序員參考手冊(cè) |
| 文件頁(yè)數(shù)： | 19/186頁(yè) |
| 文件大?。?/td> | 918K |
| 代理商： | 20665 |
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1-8
Power Management
thus drawing additional power from the DRAM devices. DRAM content is invalid when
exiting from Off mode when the disable-refresh feature is being used.
1.1.2
PMU Operating-Mode Transitions
Figure 1-1 on page 1-4 shows the élanSC310 microcontroller’s six operating modes and
the transitions that can occur between them. In this diagram, the term
by a number from 1 to 5, refers to different timer intervals of inactivity, which are set by
programming the Mode Timer registers at Indexes 83–87h. The term
programmer-specified computing activities set in the following registers:
inactivity
, followed
activity
refers to the
I
Activity Mask 1 and 2 registers at Indexes 75–76h
I
I/O Activity Address 0 and 1 registers at Indexes 8C–8Dh
I
Memory Write Activity Lower and Upper Boundary registers at Indexes 9A–9Bh
I
PMU Control 1–3 registers at Indexes A7h, AFh, and ADh
For more information, see the programming examples later in this chapter. The SUS/RES
pin is an external pin that can be triggered to cause a transition between modes.
Each power-management mode is characterized by a different clock-frequency pattern—
the CPU, system bus, and many peripheral devices have their own clocks. Several clock-
switching permutations are possible through the use of the PMU modes. The PLLs act as
sources for other clocks as follows:
I
High-Speed PLL
grammed to run at either 40, 50, or 66 MHz, yielding an internal CPU operating fre-
quency of 20, 25, or 33 MHz, respectively. The PMU state machine has controls that
can disable this clock to prevent it from being used or, in addition, turn off the PLL.
Generates the high-speed CPU/memory clock only. It can be pro-
I
Low-Speed PLL
Is divided to generate the following clocks:
— Low-speed CPU/internal system clock
— 8254 timer clock
— 8250 UART clock
— 9.2-MHz keyboard-controller clock/external SYSCLK
The PMU state machine has controls that can disable some of these clocks to prevent
them from being used or, in addition, turn off the PLL entirely.
I
Video PLL
gram control, be driven on the élanSC310 microcontroller’s X1OUT or X14OUT pins.
This signal can be used as a clock for an LCD display. The disable for this clock is
shared with the low-speed PLL. If the low-speed PLL is turned off, the video PLL is
also turned off.
Generates the clock that for a 14.336 Mhz signal that can, under pro-
As shown in Table 1-1 on page 1-6, in High-Speed PLL mode, the CPUCLK signal can be
programmed to run at 33 MHz, 25 MHz, 20 MHz, or 9.2 MHz during DRAM, local-bus,
fast-ROM, and idle cycles. In all other cases, the CPUCLK signal runs at 9.2 MHz.
In Low-Speed PLL mode, the CPUCLK signal can be programmed to run at 4.6 MHz,
2.27 MHz, 1.13 MHz, or 0.568 MHz. The CPUCLK signal cannot run at 9.2 MHz in Low-
Speed PLL mode, and it always runs at the same speed regardless of the type of cycle.
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