
Power Management
1-39
1.9.5
Resume Input Caused the SMI
If a resume input caused the SMI, the following events occurred:
1. The CPU was in the Sleep, Suspend, or Off mode.
2. A rising edge was detected by the SUS/RES input.
3. The PMU jumped directly into High-Speed PLL mode on the first refresh following the
resume input.
Note:
At this point, the next SUS/RES edge is considered a suspend input.
4. The resume input caused an SMI.
5. The SMI handler was entered and SMIs were automatically masked by the CPU until a
RES3 is executed.
1.9.6
Resume Pseudocode
1. The PMU Status 1 register at Index A2h is written in order to clear the PMU SMI
request to the CPU.
2. Platform-dependent code prepares the system for the resume operation.
3. The NMI/SMI Control register at Index A5h is read to determine if any additional SMI
events have occurred while processing the suspended SMI. These additional events
should also be processed or they will be lost.
4. When the PMU generates an SMI, a bit is set in the NMI/SMI Control register to indi-
cate to software the PMU event that generated the SMI. The NMI/SMI Control register
is written to clear this bit.
5. The bit location in the SMM RAM state-save area that contains bit 12 of DR7 (the pro-
cessor’s state) must be cleared. This handles an élanSC310 microcontroller CPU
errata where bit 12 of DR7 is automatically set prior to the SMM state save. If this bit is
not cleared in the SMM state-save area prior to the CPU executing a RES3 instruction,
the erroneous bit will be reloaded into DR7. The trace opcode (F1h) is redefined as a
softSMI. The next trace instruction then causes a soft SMI to occur.
6. The CPU RES3 instruction is executed to signal the end of the SMI routine and to arm
further SMIs.
7. The application program regains control.
1.9.7
Things to Avoid
Do not allow the suspend handler to execute RES3 until the resume keystroke occurs.
Failure to adhere to this results in control returning to the application program with the
CPU clock running for a short period of time. If application code is executed during this
time, there is a chance that powered-down peripherals will be accessed. Even DRAM
may be powered down at this point as a result of the preparation for Suspend mode.