
Configuration Registers
4-61
4.3.87
PMU Control 2 Register (Index AFh)
This register controls several PMU operations.
4.3.88
Function Enable 1 Register (Index B0h)
Bit 3
is stopped between DMA transfers.
When this bit is set, the DMA clock runs only when a DMA access is happening; it
Bit 1
outputs for the parallel-port hardware interface implemented on the system board. When
bit 1 is 0, DBUFOE is not generated during parallel-port accesses. This bit should only be
0 if the system is implemented without a system buffer. This bit must be 1 for systems that
have a system buffer and implement a parallel port with either an input buffer and output
latch, or just an output latch.
This bit is used to configure the élanSC310 microcontroller’s parallel-port control
7
0
Bit
Default
CHGON
0
CHGFUSET BL1LOWSP
0
(Reserved)
EXTIR0ACT
0
0
0
0
0
0
Bit
Name
R/W
Function
7
CHGON
R/W
Low-Speed to Doze Mode Timer register (Index 84h) unit value:
1 = 1
4 s
0 = 1
16 s
High-Speed to Low-Speed Mode Timer register (Index 83h) unit value:
1 = 1
16 s
0 = 1
512 s
1 = Set CPU clock speed to low speed (9.2 MHz) in High-Speed PLL mode
if BL1 is Low and ACIN is Low.
(Reserved)
1 = Extend CPU run time for an additional 64 refresh cycles following IRQ0
while in Doze mode. This bit is effective only if bit 3 of the MMSB Control
register at Index 74h is 1.
6
CHGFUSET
R/W
5
BL1LOWSP
R/W
4–1
0
R/W
R/W
EXTIR0ACT
7
0
Bit
Default
(Reserved)
0
X1SEL
0
EXTSMIEDG EXTSMIEN
0
DMASTCLK
0
EPPMODE
0
PPISBI
0
PPBIENB
0
0
Bit
Name
R/W
Function
7
6
R/W
W
(Reserved)
X1OUT clock select:
0 = X1OUT determined by bit 2 of Index B1h
1 = X1OUT driven by BAUDOUT
External SMI active edge
1 = Active-Low external SMI
0 = Active-High external SMI
1 = Enable external SMI
1 = DMA stop clock (Power-Save mode) enable
EPP mode enable for parallel port
Bidirectional configuration enable for parallel port
Bidirectional enable for parallel port
X1SEL
5
EXTSMIEDG
R/W
4
3
2
1
0
EXTSMIEN
DMASTCLK
EPPMODE
PPISBI
PPBIENB
R/W
R/W
R/W
R/W
R/W